synthesis using only inverting gates vs using inverting+ non-inverting gates

[alokem]

Lets consider two cases:

1) library available for synthesis contains only "inverting" gates .
2) library available for synthesis contains both "inverting" and "non inverting" gates .

What will be the outcome of synthesis in terms of delay / power / area for the above mentioned
two cases ?

 

[mail4idle2]

When inverting cells are present those will be used mostly.
So in two scenarios you have mentioned results will look same.

 

[OhaAmo]

If the inverting gates are identical, we can generally say that the second library has more flexibility in all the domains, therefore will possibly achieve better results.

 

[alokem]

When inverting cells are present those will be used mostly.
So in two scenarios you have mentioned results will look same.

Lets say , one AND needs to be implemented .For case 1 , it will be NAND->Inverter .
So there be increase in delay /area . Isn't it ?

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Lets say , one AND needs to be implemented .For case 1 , it will be NAND->Inverter .
So there be increase in delay /area . Isn't it ?

Just thinking , AND takes 6 transistors ,NAND+Inverter also takes 6 transistors . In this situation ,result
should be identical . Then why complex cells are built , isntead functionality of those could be implemented using
basic gates ? Ex :ICG .. Pl help

 

[OhaAmo]

If you are using NAND+INV, you will see that in many cases those gate will appear after placement not completely close to each other (because of other gates, dense rows and more...). Therefore you will need those 2 cells to be routed and consume more routing resources. that will surely increase your power, density and area (you will sometime need to add some buffers) with comparison to a lib that includes also AND cell.

 

[alokem]

If you are using NAND+INV, you will see that in many cases those gate will appear after placement not completely close to each other (because of other gates, dense rows and more...). Therefore you will need those 2 cells to be routed and consume more routing resources. that will surely increase your power, density and area (you will sometime need to add some buffers) with comparison to a lib that includes also AND cell.

Thanks ! Just one query regading this : Will there be any difference in results at logic synthesis stage using WLM ?