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synthesis to logical netlist with Synplify

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tleonard

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I want to use Synplify to synthesize from SystemVerilog source to a netlist that has only a few types of primitives (AND, OR, XOR, NOT -- the design should be entirely combinatorial so I shouldn't even need flops), so I can do logical analysis of the design. Is there a way to get Synplify to do that?
 

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