synthesis, STA, GLS ???

[popa]

Hi,
1.can someone help me with the meaning of each of the following:
Synthesis?
GLS?
STA?
what is the goal of each one of them?

2.I wrote a design in verilog and tested it in modelsim, now what is the next step?

Thanks.

 

[mrflibble]

So, not even synthesis results in meaningful google hits where you live? That's odd...

---------- Post added at 19:31 ---------- Previous post was at 19:28 ----------

plenty to be found on synthesis. random google hit du jour.

VHDL - Wikipedia, the free encyclopedia

"Synthesis is a process where a VHDL is compiled and mapped into an implementation technology such as an FPGA or an ASIC. Many FPGA vendors have free (or inexpensive) tools to synthesize VHDL for use with their chips, where ASIC tools are often very expensive.

Not all constructs in VHDL are suitable for synthesis. ..."