Synthesis question.. case or assign?

[jelydonut]

For synthesis, which would opt the best results or would it end up being the same..
including situations with many more cases..

assign x = (blah == 2'b00) ? a :
((blah == 2'b01) ? b :
((blah == 2'b10) ? c :
((blah == 2'b11) ? d :
16'hxxxx )));

OR

case(blah)
2'b00 : x <= a;
2'b01 : x <= b;
2'b10 : x <= c;
2'b11 : x <= d;
default : x <= 16'hxxxx;
endcase

ignoring any syntax i may have screwed up...

jelydonut

 

[horzonbluz]

You codes can't be opt to good result.
X state can't be adopted in design.

 

[gayball]

I think the second is good choice. You can use synopsys primitive to notify the synthesizer that it is a fullcase.

 

[khorram]

Most of synthesis tools generate the same codes and also delay and number of building blocks in both designs are equal.
I'd prefer the second one because it is more readable than one. But if we want to discuss about them based on synthesis concepts, both of them are equal and do not have any advantages to the other.

Regards,
KH

 

[niuniu]

I have try it in DC, they are the same. but assign X is not necessary.

 

[z81203]

I have try it in DC, they are the same. but assign X is not necessary.

Really? But AE of EDA tools told us 'case' better than 'assign', because timing.
I havn't check it, I believe you. Optimization of DC will do something.

 

[haosg]

hi, put time on more meaningful thing.

 

[haosg]

hi, put time on more meaningful thing.

 

[haosg]

hi, put time on more meaningful thing.

 

[zhangpengyu]

It's the same ,I think!

 

[haoboy]

with case is better.

 

[jelydonut]

personally i perfer the assign.. since it gets defined as a wire and you don't hafta worry about latch instantiation..

jelydonut

 

[tukken]

x is very bad for design.
you design from two script will be same

 

[jelydonut]

why is x bad in design? I haven't heard that yet..

jelydonut

 

[spauls]

Case is better, it will generate less H/w

 

[JesseKing]

i don't assign x or default x evaluation is unnecessary. dc can opt the design to the best if there is assigning x.

 

[taotaocui]

JesseKing is right.

 

[tukken]

X maybe pull FSM into don't kown situation which you don't expect in complex design, it will be danger for design.