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Synthesis question about 62.5 Mhz design in Design Compiler

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feel_on_on

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when i synthesis a design with Design compiler, if the design work in 62.5 MHz, do i ought to create_clock -period 16ns ? or i ought to create_clock -period more short than 16ns ? There should keep a slack on work frequency ?
 

hunter694

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synthesis question

In general, it is better to give tighter restrictrictions to the tool than you really need.

It helps make the synthesis tool more pro-active in terms of meeting timing constraints and also gives you a sort of engineering margin (if your freq. is 62.5 MHz, you dont need a design that cannot run at 62.6 MHZ!!).

However, 60MHz+ is a pretty high frequency so don't give too tough a clock constraint or the tool might be unable to converge on a solution.
 

barkha

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synthesis question

Hi,

Usually we are taking 10-15% margin. If suppose design needs to work in 62.5 MHz , It will be better if you will synthesize with 72.5 MHz.
 

r63511

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synthesis question

Well, it depends on the library you're using. If you use 180nm, 60MHz+ might be a tough freq, but you're using 130nm, 90nm or smaller, you may set a tighter constraints. The actual constraint also depends on the clock uncertainty, latency, cell delay, etc that your team can meet.
 

sree205

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synthesis question

Are there any restrictions to the area ? when i synthesized using DC, i did 'set_max_area' to be 0.

after i got an area report which said that the constraint is violated by so much of area, i gave that as the max_area in the updated constraint.

Is this how it should be done ? iteratively ?
 

rameshsuthapalli

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synthesis question

Hi All,

the design operation frequency is depends on the amount of the complexity that is present in the design and then only it depends on the technology.but of the synthesis point of view it is better to have the 15% margen on the clock because a good design should have the +ve slack when it is operating at the rated speed.which would eliminate the problems at later stages.

regards,
ramesh.s
 

michael_chen

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Re: synthesis question

i think you should make period of create_clock less than 16n second. Because after DC, p&r and cts and other design flows will add a little delay.
 

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