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when i synthesis a design with Design compiler, if the design work in 62.5 MHz, do i ought to create_clock -period 16ns ? or i ought to create_clock -period more short than 16ns ? There should keep a slack on work frequency ?
In general, it is better to give tighter restrictrictions to the tool than you really need.
It helps make the synthesis tool more pro-active in terms of meeting timing constraints and also gives you a sort of engineering margin (if your freq. is 62.5 MHz, you dont need a design that cannot run at 62.6 MHZ!!).
However, 60MHz+ is a pretty high frequency so don't give too tough a clock constraint or the tool might be unable to converge on a solution.
Well, it depends on the library you're using. If you use 180nm, 60MHz+ might be a tough freq, but you're using 130nm, 90nm or smaller, you may set a tighter constraints. The actual constraint also depends on the clock uncertainty, latency, cell delay, etc that your team can meet.
the design operation frequency is depends on the amount of the complexity that is present in the design and then only it depends on the technology.but of the synthesis point of view it is better to have the 15% margen on the clock because a good design should have the +ve slack when it is operating at the rated speed.which would eliminate the problems at later stages.