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Synthesis problem .....Can anyone help me.................

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akp494

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I'm using index to access some bits of a shift register as this index changes values depending on some conditions.
in VHDL the piece of code looks like this:
a<= reg(ptr+1 downto ptr) where 'a' is a two bit vector.

When I try to synthesize the above piece of code,Synopsys DC says a constant is expected as the index.

In my opinion the synthesis tool should be upgraded to infer these kind of implementations. Here 'reg' is defined, "a" is defined and also "ptr" is defined and hence the tool shouldn't ideally see a problem in implementing this.

Let me explain the problem in a different way.

Suppose I have the following signal declarations.

signal reg : std_logic_vector(15 downto 0);
signal ptr : integer;
signal a : std_logic_vector(1 downto 0);

Then at some place in the code if I say

a<= reg(ptr+1 downto ptr)

Now if I try to synthesize this code using DC it is giving an error at the above statement showing the following comment.
"A Constant is expected as index"


Is there any work around for this?? Is it the problem with the tool.
 

jazz_roa

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Re: Synthesis problem .....Can anyone help me...............

You may use the following way if ptr is a 4-bit vector

case (ptr)
when "0000" => a <= reg(? downto ?);
when "0001" => a <= reg(? downto ?);
...
when others => ...
endcase
 

akp494

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Re: Synthesis problem .....Can anyone help me...............

Hello Jazz
I don't want to test for all the combinations of "ptr". Because it will blow up my code. So is there any way a tool can recognize such a kind of indexing??
 

atuo

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Re: Synthesis problem .....Can anyone help me...............

you can try the BC or Synplify because the tools support the behavior synthesis.
 

foster_cn

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Re: Synthesis problem .....Can anyone help me...............

why have to synthesis behavior design?
 

hawk

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Re: Synthesis problem .....Can anyone help me...............

no need to synthesize behavioral design.
this will not benefit.
 

hawk

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Re: Synthesis problem .....Can anyone help me...............

you are mixing with the bits sizes.
this will confuse dc.
you must use the exact size of bits which you will use
in the shift reg.
dont give extra.
& yes, you must declare all options (use fullcase/parallel case.)

you can see shift reg examples in this forum/web
good luck.
 

hawk

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Re: Synthesis problem .....Can anyone help me...............

also use a linter before going to dc.
it also can help.
 

faisalali

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Re: Synthesis problem .....Can anyone help me...............

You can't do this in this way. Note that a<= reg(ptr+1 downto ptr) means that physical connections between a and reg changes depending on the value of ptr. Once a design is synthesised these physical connection become constant. You want that these physical connections would change during real time, when the device is working which is impossible. In VHDL such statement are only used for static purposes for e.g when you use generic. Alternatively, what you can do is : you should use a multiplexer between a and reg and control the flow of data between a and reg by changing the select input of the multiplexer.
 

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