[Synthesis] Optimization stages

[ivlsi]

Hi All,

Logic synthesis has several optimization stages... Here are some of them:
- Translation of RTL to Gates (RTL-to-Generics Lib)
- Mapping of Generics to Technology library cells
- Timing Optimization (while meeting DRC)
- Area Optimization (while meeting DRC)
- Power Optimization (while meeting DRC)

Have I missed some stages or mixed them up?

Thank you!

 

[englishdogg]

not sure if i understand well... synthesis i would say is one stage in itself for a design cycle...
Even if we break it up in stages at all stages the priority is same meeting timing, power and area constraints

In simple terms deliver a best optimized netlist from RTL which achieves the PPA.
If you trying to set stages depending on the synthesis script - this would vary depending on the synthesis tool used...
Still Timing opto or area opto or any other algorithm will be called at all major compile / map stages to achieve a best PPA

 

[micpro]

Hi All,

Logic synthesis has several optimization stages... Here are some of them:
- Translation of RTL to Gates (RTL-to-Generics Lib)
- Mapping of Generics to Technology library cells
- Timing Optimization (while meeting DRC)
- Area Optimization (while meeting DRC)
- Power Optimization (while meeting DRC)

Have I missed some stages or mixed them up?

Thank you!

Yes, I'd add a stage: You can use the post-layout SPICE netlist of a synthesized design and tune the device widths (in a narrow range of course). The optimization targets are similar to those you mentino (power, timing, area), but the method and tools are of course very different from the optimization on RTL level where you change only the topology and select cells from a finite set. The impact of this geometry-optimization can be very dramatic; full-custom digital design is all about it.

 

[ivlsi]

which achieves the PPA

What is PPA?

- - - Updated - - -

tune the device widths

Are you about the floorplaning?

The impact of this geometry-optimization can be very dramatic; is all about it.

Could you give some more info about the full-custom digital design?

Thank you!

 

[micpro]

Are you about the floorplaning?
Could you give some more info about the full-custom digital design?
Thank you!

Not floorplanning, but the individual transistor's widths. It's an incremental change: make some MOS 5% wider, another one 3% more narrow, ... and simulate the circuit with some fast spice simulator. Find the optimal change of device widths. Disclaimer: my company (MunEDA) is working in this field.

One example presentation: GH Oh (Altera): Circuit optimization with WiCkeD design tools, MUGM 2011. shows two examples of digital circuit optimization when designing FPGA:
a) delay chain: reduce delay spread over corners and reduce area by 23%
b) lookup table: reduce area by 20% without increasing critical path's delays

You can register to see MUGM presentations at **broken link removed**

 

[tariq786]

Not floorplanning, but the individual transistor's widths. It's an incremental change: make some MOS 5% wider, another one 3% more narrow, ... and simulate the circuit with some fast spice simulator. Find the optimal change of device widths. Disclaimer: my company (MunEDA) is working in this field.

One example presentation: GH Oh (Altera): Circuit optimization with WiCkeD design tools, MUGM 2011. shows two examples of digital circuit optimization when designing FPGA:
a) delay chain: reduce delay spread over corners and reduce area by 23%
b) lookup table: reduce area by 20% without increasing critical path's delays

You can register to see MUGM presentations at **broken link removed**

Dude where is the registration page ? I am not able to find it

 

[englishdogg]

PPA - power, performance and area