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synthesis of I&Q clock signals using 2 PLLs

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Eugen_E

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Hello,

I want to ask if its possible to generate quadrature clock signals using 2 input signals with a small phase shift between them, applied to 2 PLLs like in the image.
The frequency dividers implemented as cascaded flip-flops should be reset at the start, to ensure proper phase shift, or the PLLs wil take care of this?

Thank you.
 

VVV

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I suggest you start from twice the frequency and divide it by two, using two flip-flops, one triggerred on the rising edge, the other on the falling edge of the input signal. You will obtain two signals which are always 90 deg out of phase.
 

    Eugen_E

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Eugen_E

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Thanks for the reply.

I know about obtaining quadrature signals using 2 flip flops and an inverter, but I want to use the above circuit - with PLL .

The maximum frequency of the VCO in the PLL is limited, and I can't aford the frequency division with 2. Generating 2 signals with 2.8 deg phase shift is easier, because is done in software - a software DDS runing on a processor, and I need PLL anyway, to multiply the frequency.
Please tell me if this will work, and if I should reset the frequency dividers at the start.
 

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I am not sure I understand the comments about the frequency being too high, since you would no longer need the PLLs.

Anyway, I do not understand why you need the 2.8 deg phase shift, if you need the signals to be in quadrature. Shouldn't that be 90 deg?
Other than that, I think the approach will work.
 

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