Synthesis Interview questions

[limitless_21]

hi all

here are a few questions listed in which i was unable to answer during a interview......can anybody please help me on this ????

• What are the various factors that need to be considered while choosing a technology library for a design?
• What will happen to a design that is synthesized without any constraints?
• How do you perform Synthesis activities in Multi vt libraries?
• What is the difference in PT timing analysis during post and pre layout designs?
• What are the difference you find when you switch from 130nm to 90nm?
Why max and min capacitance required?
What is Metastability? How to overcome metastability? If metastable condition exists which frequency you will use as clock- faster or slower? Why?

it will be very helpfulif anyone can give me basic scenario regarding the questions above.....

 

[vijayR15]

hai limitless_21,

• What are the various factors that need to be considered while choosing a technology library for a design?
The technology lib should have all the cells which u are having in the RTL. Additionally It should have the filler,Tie, endcap and decap cells. Then the cells should have information of proper timing information, pin direction, trasition value, power and area in lib file.

• What will happen to a design that is synthesized without any constraints?
Without any constaints means that u are not taking care of the timing . So u dont know how much frequency should ur chip work. Once u set freqency U should also check for setup and hold violation. If there is a setup violation then your chip will function slow.If u have hold then ur chip will not work as u expect. So without constraints u will get only gate level netlist file(i.e mapping the normal gates with the gates in the lib).

• How do you perform Synthesis activities in Multi vt libraries?
For area calculation choose the worst case lib(low voltage) for synthesis and for power calculation choose the best case lib(high voltage) for synthesis. default use worst case lib for Synthesis. Also worst case lib for setup and best case lib for hold.

• What are the difference you find when you switch from 130nm to 90nm?
In 130nm Cell size will be bigger , it consumes more area and hence floorplan will be bigger. Also It consumes more power. 90nm consumes less area and less power compared to 130nm.

Why max and min capacitance required?
The maximum and minimum capacitance is the total capacitive load that an output pin can drive..The min_capacitance rule specifies the minimum load a cell can drive. max_capacitance is available only for output pins. These things will be present in lib file.

Ex:-
pin (Z) {
direction : "output";
related_bias_pin : "VDDB VSSB";
max_capacitance : 0.334971 ;
max_fanout : 20 ;
…
timing () {
cell_degradation (constraint) {
index_1 ("1.0, 1.5, 2.0") ;
values ("1.0, 1.5, 2.0") ;
}
}


Hint :-
If you have more output capacitance load then it will take more time to charge /discharge to/from a particular logic level. It means that the delay of the cell is more.


What is Metastability? How to overcome metastability? If metastable condition exists which frequency you will use as clock- faster or slower? Why?

Metastable: A state which exist between either "valid" digital logic state {an undefined voltage}

Connecting two or more flip flops in series can also reduce the probability of metastability occuring.

In flip flops it occurs mainly if the input signal occurs temporally close to the clock signal or it held its state for a shorter time than necessary, i.e. setup and hold time violations.