synthesis...how to mark a gate as black box

[satishgra]

Hi,

I have a half adder and want a synthesized netlist out of it where in all the nand gates {for example} need to be considered as black boxes. I want to use the RC netlist directly in the final resulting netlist.

Basically, I am looking at using HSIM for co simulation and then use prime time to generate the power numbers. Unfortunately, for PT to run, it needs a synthesised netlist.

This is just a small example and I have a huge design where I want to implement the same procedure

Regards,
Satish

 

[asic_service]

If you just want the synthesis tool don't use some logic gate in the cell library, you can use the set_dont_use command in DC.