Synthesis and Structured ASICs

[jelydonut]

When targeting a structured asic, is there a technology file that is provided by the vendor or some other way to find out approximate gate counts?

I'm doing a SOC and would like to know what the counts are of the currently completed modules to know what kind of space i have available to me.

jelydonut

 

[arunragavan]

well there are datasheets and other informations regaring an FPGA.. but as of ASIC the vendors wud have to provide the details of basic gate count and other parameters as they are very important from the designer's point of view..
ASIC be it fully customed or semi customed they are designed only by the user and then as according to the design the manufacturer brings out the final product.. ASICs are more or less like IPs.. somethin of that sorts.. u wud definetly have all details includin the floor plannin if u had bought it from the vendor..

with regards,

 

[aravind]

"i cant understand ur question exactly . ur question is u wanna count area of ur design and gate count of deisgn?" jelydonut .
if u design sturctured asic u must give approx. aspect ratio for u design to acceive optiumun area for module of ur design