If you have an incomplete if statement, the synthesis tool will generate a latch. As you can see in the code, last else statement prevents to make a latch. You should assign a default value to the DOUT.
process(CSN, RDN, ADDR, DO_higher, DO_lower)
begin
if (CSN='0' and RDN='0' and ADDR()='1') then
DOUT <= DO_higher(SAMPLE_WIDTH-1 downto 0);
elsif (CSN='0' and RDN='0' and ADDR()='0') then
DOUT <= DO_lower(SAMPLE_WIDTH-1 downto 0);
else
DOUT <= DEFAULT_VALUE;
end if;
end process;
Regards,
KH