Oct 2, 2012 #1 M macgradywk Junior Member level 2 Joined Sep 24, 2012 Messages 23 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,443 Here is my testbench with syntax error, unexpected wire, expecting";" in line 2, what's wrong? code: module test_project1 wire clk,reset; reg [7:0] port1; wire [8:0] port2; reg eof; integer project1; initial project1=$fopen("proj.dat","rb"); always@(posedge clk) begin eof=feof(project1); if(eof==0) $fscanf(project,"%b",port1); else begin $fclose(project1); $finish; end end init my_init(clk,reset); project1 my_project1(port2,port1,clk,reset); endmodule
Here is my testbench with syntax error, unexpected wire, expecting";" in line 2, what's wrong? code: module test_project1 wire clk,reset; reg [7:0] port1; wire [8:0] port2; reg eof; integer project1; initial project1=$fopen("proj.dat","rb"); always@(posedge clk) begin eof=feof(project1); if(eof==0) $fscanf(project,"%b",port1); else begin $fclose(project1); $finish; end end init my_init(clk,reset); project1 my_project1(port2,port1,clk,reset); endmodule
Oct 2, 2012 #2 dftrtl Banned Joined Feb 1, 2011 Messages 347 Helped 76 Reputation 152 Reaction score 74 Trophy points 1,308 Location Bangalore Activity points 0 Module without ports has to be end with semicolon like below line module test_project1;