Syntax error near "when"

[mo.khairy.mo]

hi all
what's the error in this vhdl code

when (opcode = addu) =>
	   I0 : int_2s_add_sub
      PORT MAP (
         clk           => clk,
	 enable      => '1',
         rst           => rst,
         opa         => opa,
         opb         => opb,
         M	       => '0',
         OVF 	       => flags(5),
         opc 	       => opc
      );

if i need to port map some components depend on conditions how can i do it?


thanks in advance

 

[balavinayagam]

use block statement . depending on the "guarded " condition assignment will take place

 

[devas]

Hi,

Use the generate statement instead of your when:

g0: if (opcode = addu) generate
I0 : int_2s_add_sub
PORT MAP (
clk => clk,
enable => '1',
rst => rst,
opa => opa,
opb => opb,
M => '0',
OVF => flags(5),
opc => opc
);
end generate;

 

[mo.khairy.mo]

thanks all
@balavinayagam
could u please support me with an example
@devas
i try what u suggest and i have the following error
"generate condition is not constant"
how can i fix it ?!

 

[devas]

Hi,

That's a problem. The generate condition must be static, i.e. it cannot include signals. I was forgotten this. I do not know if you can change the condition so it becomes static. Maybe the block suggestion will work but I have never used block statements so I have no idea.

Success, Devas

 

[mo.khairy.mo]

Hi,

please could u explain what do u mean with static?!