[SOLVED] syntax error generate statement

[nomigul]

I am using ISE Design Suite 14.5 to try and synthesize a design and I keep getting the following errors when trying to use a generate block

module genvar(x,y,z
    );
parameter n = 4;
input [n-1:0]x,y;
output [n-1:0]z;
genvar i;
generate
for (i=0; i<n; i=i+1)
begin
xor g1(z1(i),x(i),y(i));
end
endgenerate
endmodule

Error:
Line 21: Syntax error near "genvar".

 

[FvM]

I guess problem is module name equal to reserved name genvar.

 

[wwfeldman]

not familiar with ISE Design Suite 14.5
however:
module genvar has 3 parameters, and you use genvar i inside it
i would expect using module genvar requires 3 parameters, and a different syntax
also, it appears(?) that you are making genvar recursive

 

[jdb2]

I am using ISE Design Suite 14.5 to try and synthesize a design and I keep getting the following errors when trying to use a generate block

module genvar(x,y,z
    );
parameter n = 4;
input [n-1:0]x,y;
output [n-1:0]z;
genvar i;
generate
for (i=0; i<n; i=i+1)
begin
xor g1(z1(i),x(i),y(i));
end
endgenerate
endmodule

The first problem with your code is that you're using the reserved keyword "genvar" for the module name -- you'll have to use a different name. The second problem is the lack of a name for the for loop block in the generate statement. Furthermore the expression "xor g1(z1(i),x(i),y(i));" is a syntax error. You should instead be using brackets for bit selects. Also, the name "z1" is undeclared. The corrected code should be :

---

Code Verilog - [expand]
1
2
3
4
5
6
generate
for (i=0; i<n; i=i+1)
begin : replace_with_name_of_your_choice
xor g1(z[i],x[i],y[i]);
end
endgenerate

---

Also, unless you plan on having multiple generate statements that use the same generate variable, it's usually better coding practice to declare the genvar variable within the generate...endgenerate block.

Hope this helps,

jdb2

--- Updated Oct 26, 2021 ---

Furthermore the expression "xor g1(z1(i),x(i),y(i));" is a syntax error. You should instead be using brackets for bit selects. Also, the name "z1" is undeclared.

Unless, of course, "x" and "y" are functions to be invoked on the loop variable, but, in that case you'd have a name collision between said functions ( which aren't declared in your module snippet ) and the module's input and output nets. A syntax error in all cases would be the "z1" in the xor primitive's output -- there should be a net there.

jdb2