vdtanna
Newbie level 1
I am running synplify_pro and I have automaticaalt generated Fasle and Multicycle paths are other tool. When I try to apply those constaint to synplify pro in .sdc file and do constraint check many of them flags error due to various reason.
(1) FAM explorer changed register bitwidth and name also during FSM re-encoding.
(2) Ig any register is driven inside generate block it puts extra tags in hierarchical name of the register.
(3) If any register is driven by constant it changes that register to net during compilation.
(4) If some nets get concatenated and make a bus. (assign a = {b,c,d}). Synplify pro doesn't identify path "-through" resultant bus. It treats all the concatenated nets independently.
(5) If in hierarchy net is assigned to net in instantiated module, it keeps only toplevel net when it flatterns it. So any false or multi cycle path going -through removed net is not getting accepted?
For all these problems, synplicity flags that eitehr start point or end point object doesn't exist.
Any known resolution of these problems rather than changing names manually?
(1) FAM explorer changed register bitwidth and name also during FSM re-encoding.
(2) Ig any register is driven inside generate block it puts extra tags in hierarchical name of the register.
(3) If any register is driven by constant it changes that register to net during compilation.
(4) If some nets get concatenated and make a bus. (assign a = {b,c,d}). Synplify pro doesn't identify path "-through" resultant bus. It treats all the concatenated nets independently.
(5) If in hierarchy net is assigned to net in instantiated module, it keeps only toplevel net when it flatterns it. So any false or multi cycle path going -through removed net is not getting accepted?
For all these problems, synplicity flags that eitehr start point or end point object doesn't exist.
Any known resolution of these problems rather than changing names manually?