Synplify_pro Synthesis Warning - Found combinational loop during mapping

[atifhashmi]

Hi all,

I am trying to synthesize the following verilog module using synplify_pro

module poissonEncoderWithLFSR(clk, set, next, seed, dataIn, encOut);
	parameter NUM_BITS_IN = 12;
	parameter NUM_BITS_LFSR = 8;
	
	input clk,set,next;						  
	input [NUM_BITS_LFSR-1:0] seed;
	input [NUM_BITS_IN-1:0] dataIn;
	output reg encOut; 
	
	wire [NUM_BITS_LFSR-1:0] randVal;
	wire [NUM_BITS_IN-1:0] zeroPaddedRandVal; // making the randval and dataIn of the same bit length	 
	wire result;
	
	lfsr_8bit lsfr_8bit_0(.clk(clk),.set(set),.next(next),.seed(seed),.randVal(randVal));	 
	
	assign zeroPaddedRandVal = {{(NUM_BITS_IN-NUM_BITS_LFSR){1'b0}},randVal[NUM_BITS_LFSR-1:0]};	  
	assign result = (dataIn > zeroPaddedRandVal)?1'b1:1'b0;	  					 
	
	always@(posedge clk)
		begin		
			if(set) encOut <= 0;
			else if(next) encOut <= result;
			else encOut <= encOut;
		end
endmodule

module lfsr_8bit(clk,set,next,seed,randVal);
	input clk,set,next;				  
   	input [7:0] seed;
	output reg [7:0] randVal;	
	
	wire linearFeedback = randVal[7]^randVal[5]^randVal[4]^randVal[3]; 
	
	always@(posedge clk) 
	begin		
		if(set) randVal <= seed;
		else if (next) randVal <= {randVal[6:0],linearFeedback};
		else randVal <= randVal;
	end			
endmodule

When I synthasize it using synplify_pro, I get the following warnings during the Map and Optimize phase.

W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[0]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[1]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[2]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[3]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[4]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[5]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[6]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[7]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[0]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[1]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[2]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[3]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[4]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[5]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[6]
@W:BN137 : poissonencoderwithlfsr.v(18) | Found combinational loop during mapping at net randVal_i[7]
@W:MT420 :  | Found inferred clock poissonEncoderWithLFSR|clk with period 6.03ns. Please declare a user-defined clock on object "p:clk"

I have spent quite some time to see where the combinational loop is but have been unsuccessful. Any suggestions? Am I missing something? I will really appreciate any help in this matter.

Thanks

 

[aruipksni]

mabee you should try and write your code like this :
module lfsr_8bit(clk,set,next,seed,randVal);
input clk,set,next;
input [7:0] seed;
output reg [7:0] randVal;

wire linearFeedback = randVal[7]^randVal[5]^randVal[4]^randVal[3];

always@(posedge clk)
begin
if(set) begin
randVal <= seed;
end
else if (next) begin
randVal <= {randVal[6:0],linearFeedback};
end
else
randVal <= randVal;
end
endmodule

 

[atifhashmi]

nope! Still getting the same warning.

Thanks for the suggestion though!

 

[aruipksni]

nope! Still getting the same warning.

Thanks for the suggestion though!

It run fine on xilinx ise. So i guess it is something else.