omara007
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Hi folks
I am facing a problem while using Synplify to synthesize my VHDL design to Xilinx Spartan-3A DSP .. the problem is simply that when I chose my top-level block to be synthesize, Synplify goes thru the compilation process only and generates a netlist that contains nothing but the interfaces of my top-level block .. it doesn't go thru hierarchy or map my lower-level modules to Xilinx primitives ..
On the other hand, when choosing to synthesize a lower-level hierarchy (by itself), Synplify works fine and maps the compiled RTL to Xilinx primitives .. given that lower-level block doesn't contain any smaller modules ..
So, what could be the reason for this problem ? .. is it something that I need to mention regarding the hierarchy ?
Added after 4 hours 6 minutes:
I found the following in the map report:
Is this the reason why I'm not getting such a block mapped during synthesis ?
same with the rest of lower-level modules!!
P.S. I have all component statements coded in a components package, not inside the top-level module.
I am facing a problem while using Synplify to synthesize my VHDL design to Xilinx Spartan-3A DSP .. the problem is simply that when I chose my top-level block to be synthesize, Synplify goes thru the compilation process only and generates a netlist that contains nothing but the interfaces of my top-level block .. it doesn't go thru hierarchy or map my lower-level modules to Xilinx primitives ..
On the other hand, when choosing to synthesize a lower-level hierarchy (by itself), Synplify works fine and maps the compiled RTL to Xilinx primitives .. given that lower-level block doesn't contain any smaller modules ..
So, what could be the reason for this problem ? .. is it something that I need to mention regarding the hierarchy ?
Added after 4 hours 6 minutes:
I found the following in the map report:
Code:
Removing instance rx2450_1.rcip_vr_parallel_6 of black_box view:work.rcip_vr_parallel(syn_black_box) because there are no references to its outputsIs this the reason why I'm not getting such a block mapped during synthesis ?
same with the rest of lower-level modules!!
P.S. I have all component statements coded in a components package, not inside the top-level module.