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synopsys vcs question

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peen1

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vlogan verilog

Gentlemen,

I am trying to switch from modelsim to vcs. In modelsim I complile different sections of my design in different libraries and call these libraries during simulation.

1) My question is that how do I create libraries in vcs.

2) How do I call these libraries during the simulation run

Thanks
 

vcs vlogan

peen1 said:
Gentlemen,

I am trying to switch from modelsim to vcs. In modelsim I complile different sections of my design in different libraries and call these libraries during simulation.

1) My question is that how do I create libraries in vcs.

2) How do I call these libraries during the simulation run

Thanks
Hi,
What is your flow like? Is it pure Verilog/SV? If so you don't have to take that pain of going thro' library etc. (Which is BTW more of VHDL centric stuff). I understand there are some positives about that approach, but given the amazing incremental compile in VCS, I couldn't see that need. Simple vcs -f flist will do it for you!! (flist having all files).

If you are a VCS-MX user, look at vlogan - pretty close to what vcom/vlog does.

HTH
Ajeetha, CVC
www.noveldv.com
 

vlogan vs vcs

thanks Ajeetha for the reply,

I have verilog source files which use alot of `define parameters. The stimulus files use the same parameter names as the design files but the values of these `defines are different for the stimulus and the design. So either I can change code and re-name parameters or compile the stimuls and the designs into different libraries. I made different libraries for modelsim and want to do the same for vcs
 

vlogan synopsys

peen1 said:
thanks Ajeetha for the reply,

I have verilog source files which use alot of `define parameters. The stimulus files use the same parameter names as the design files but the values of these `defines are different for the stimulus and the design. So either I can change code and re-name parameters or compile the stimuls and the designs into different libraries. I made different libraries for modelsim and want to do the same for vcs
Hi Peen1,
Sorry to say, but it looks to like a bad coding practice to rely on `defines to be different across design/tb. However, 1defines can be re-defined (simply re-define it) or `undef etc. So you should still be able to use it in VCS smoothly. If not convinced, post a dummy example of what you would like to see, such as

design.v
tb.v

Show us how you would like say `ABC to be different in design & tb, some one may be able to assist you.

Regards
Ajeetha, CVC
 

vcs mx

Hi boy,
Why you swith modelsim to vcs?I don't think it has any advantage,for me,all simulation tool are the same,but modelsim is cheaper than vcs.


:?:
rake
 

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