Synopsys Primetime Error

[tonelow]

Hello,

I am a (student) researcher working with Synopsys EDA software packages for the first time. I have successfully constrained and compiled a circuit benchmark with Design Compiler (and extracted back-annotated saif), PAR with IC Compiler ( and extracted parasitics), simulated switching behavior with VCS (forward annotated saif), and am currently analyzing timing and power with PrimeTime. I have many RC-004 warnings (same warning for different arcs) which I cannot find any documentation about and was hoping somebody could point out what I am missing. I am using Synopsys University 28nm Standard Cell Library and I am not sure what details to post, so I will first start with just the warning itself:

Warning: Failed to compute C-effective for the timing arc through port line2 (min-rising) because the library data indicates a non-positive drive resistance. [r/f inp_slew - 0/0, out_cap = 6.68228 (lib units) ]

Thank you,
Tony

 

[yadavvlsi]

This warning is issued when the slope (relationship) between the driver cell delay and the effective load on the driver cell is negative.

Most ASIC vendors use input net transition and total output net capacitance as the tabular indexes for calculating output net transition and cell delay. When the input net transition is constant and the total output net capacitance increases, the output net transition and cell delay should also increase. If it does not (either cell delay or the output net transition stays constant or decreases while output the net capacitance increases), PrimeTime issues the above warning.

To find out whether the slope is negative or positive, follow these steps:

1) Do report_delay_calculation on the cell in question. This will provide information on input transition time and total output capacitance value.

2) Create a small design using only the gate that PrimeTime is issuing thewarning about.

3) After you back-annotate the DSPF file, use set_input_transition and set_capacitance to emulate the scenario.

4) Do report_delay_calculation from the input to the output pin of the cell.

5) Increase the total output capacitance by 1 percent.

6) Repeat steps 4 and 5, and you should see one of the following results:

An increase in total output net capacitance but no increase in output transition time or cell delay
An increase in total output net capacitance but a decrease in output transition time or cell delay

If you determine that the information in the library is incorrect, take these steps:

1) Fix the minimum and maximum transition and capacitance design rule checking (DRC) violations, if any. (Doing so will resolve any interpolation-related or extrapolation-related issues.)

2) Make sure that the trip-point variables are set correctly.

You can check this on solvent.

 

[tonelow]

Excellent. Thank your the very prompt and informative response, I will try these steps and attempt to validate the information in the library. Much appreciation!

Best,
Tony