GurinderPsingh
Newbie
Hi I am new to NanoTime
I am getting an error while link_design
Start netlist compilation at Fri Oct 23 15:55:57 2020
ERROR:NetComp:0x30201005:can not open file /home/gurinderpsingh/Synopsys/hspice/final_test/nanotime.sp.
Error: Compiling netlist failed. (NLNK-002)
0
and spice file is
I am getting an error while link_design
Start netlist compilation at Fri Oct 23 15:55:57 2020
ERROR:NetComp:0x30201005:can not open file /home/gurinderpsingh/Synopsys/hspice/final_test/nanotime.sp.
Error: Compiling netlist failed. (NLNK-002)
0
Code:
set search_path {/home/gurinderpsingh/Synopsys/hspice/final_test}
set library_path {/home/gurinderpsingh/Synopsys/hspice/final_test}
set link_path {* /home/gurinderpsingh/Synopsys/hspice/final_test/tcbn65gplusbc.db}
set oc_global_voltage 2.5
register_netlist -format spice {nanotime.sp tech.sp}
link_design InverterTest
report_port
set input_ports {IN_1 IN_0}
set_port_direction -input $input_ports
set output_ports {OUT_1 OUT_0}
set_port_direction -output $output_ports
report_port
report_design
report_net
report_cell
create_clock -name MCLK -period 10.0
report_clock
match_topology
report_transistor_direction
report_topology
check_topology
set_input_delay -clock MCLK -rise 1.0 {IN_1 IN_0}
set_input_delay -clock MCLK -fall 1.0 {IN_1 IN_0}
set_input_delay -clock MCLK -add_delay 1.0 {IN_1 IN_0}
report_port -input_delay
set_output_delay -clock MCLK 0.0 {OUT_1 OUT_0}
report_port -output_delay
check_design
trace_paths
report_paths -max -max_paths 10
exitand spice file is
Code:
set search_path {/home/gurinderpsingh/Synopsys/hspice/final_test}
set library_path {/home/gurinderpsingh/Synopsys/hspice/final_test}
set link_path {* /home/gurinderpsingh/Synopsys/hspice/final_test/tcbn65gplusbc.db}
set oc_global_voltage 2.5
register_netlist -format spice {nanotime.sp tech.sp}
link_design InverterTest
report_port
set input_ports {IN_1 IN_0}
set_port_direction -input $input_ports
set output_ports {OUT_1 OUT_0}
set_port_direction -output $output_ports
report_port
report_design
report_net
report_cell
create_clock -name MCLK -period 10.0
report_clock
match_topology
report_transistor_direction
report_topology
check_topology
set_input_delay -clock MCLK -rise 1.0 {IN_1 IN_0}
set_input_delay -clock MCLK -fall 1.0 {IN_1 IN_0}
set_input_delay -clock MCLK -add_delay 1.0 {IN_1 IN_0}
report_port -input_delay
set_output_delay -clock MCLK 0.0 {OUT_1 OUT_0}
report_port -output_delay
check_design
trace_paths
report_paths -max -max_paths 10
exit
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