Synopsys .lib generation help

[rakeshnunna]

synopsys lib

hi,

I want to create .libs for custom IO cells and some analog blocks. Idea is to use this .libs in the Astro for timing driven P&R. Guys do u know any methadology how this can be done.

Thx in Advance

 

[spauls]

.lib generation

Dont use ASTRO for generation , use Encounter for lib generation.

 

[rakeshnunna]

synopsys liberty

Hi spauls,

In dont have encounter as in my company we have Synopsys flow and I want to use the .libs in Astro, not generate using Astro

 

[rajesh9999]

synopsys .lib

Generating .lib file is not easy. You need to run several spice runs on GDSII (layout) of the cell/macro. Statistically reject the ones that fall outside 2 std deviations. This you have to do for various input cofigurations/input slews/output loads and be able to put the results of spice run outputs (ie delay values) of these several hundreds of spice runs formatted in .lib style using perl scripts. This is best left to professionals (library vendors or library team in the company). You have to ask them for .lib, not try to create yourself.

 

[aravind.b]

synopsys lib file

generating .lib file is not easy. and we cannot generate .lib by using Astro, by using spice (h-spice from synopsys) simulation we can generate the .libs

 

[rakeshnunna]

.lib file synopsys

For all my digital blocks I am having .lib coming from the vendors. I am having some

custom IOs in the design. These custom IO are similar to the regualr TSMC IOs but

have some extra pins(pins cap is available) .I want to create .lib for these so that I

can give pin cap values to astro.

 

[rameshsuthapalli]

lib file generation

Hi,

there are some tools which will convert the spice timing information into the *.lib formate which will be supported by the tools.

Regards,
Ramesh.S

 

[username1]

Hi all - I am also looking for a good way to generate .lib files for mixed-signal blocks like PLLs, ADCs, etc. Does anyone have recommendations on good approaches and tools for this? Thanks!!

 

[jpvSoccer]

Hi, if you know that there will only be small changes you could do the following:
copy yourReal.lib into libHeader.lib
open libHeader.lib and locate the first cell description

 

[username1]

OK thank you jpvSoccer. I agree hand editing may be necessary. Do you know any good tools that can be used in addition to hand editing? Cadence SoC Encounter allows generation of top level .lib files, but a separate software tool is probably required to generate the .lib for the individual analog components of the larger system.

 

[jpvSoccer]

woops...hit wrong key...

Hi, are you ready for a ****?

If you know that there will only be small changes, you could do the following:

copy yourReal.lib into libHeader.lib
open libHeader.lib and locate the first cell description
delete everything from the first cell to the last line and save the file
change the library name (near the top) to myNewCell

copy yourReal.lib into myCell.lib
open myCell.lib and locate the cell that is similar to your new cell
delete everything above this cell
goto the end of the cell and delete everything below this cell

modify myCell.lib to reflect your changes

copy libHeader.lib into myNewLib.lib
open myNewLib.lib and include the updated myCell.lib
be sure you "end" the file properly

now test to be sure you have the correct syntax in your file

 

[username1]

OK thank you. If anyone can recommend commercial software or methodologies used at large companies, that would be great.

 

[jpvSoccer]

Hi,

check out liberty ncx from Synopsys

 

[bharat123]

we have used ELC (encounter library characterizer ) for .lib creation and its really nice one and used by many big brands!

 

[username1]

I have used ELC too - it works well for digital standard cells, but is not designed to generate .lib files for mixed-signal blocks like ADCs, PLLs, etc.

 

[raju3295]

u can use PT for lib generation,
it is known as Extract timing model,

 

[nav_vlsi]

you can do that easily in PT-PX provide you have verilog, sdc & spef files
your pt script will look like this .

read_verilog
read_parasitics
source sdc
set operating conditions
extract_model

please do some home work & create a proper pt script.
This is just to give an idea for problem, This piece of script is incomplete.