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Synopsys IC Compiler: Open Nets Error

Brina9797

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Hi, do anyone know how to solve the open nets ( Logical Net VSS is open) error?

I obtained the error message attached below in LVS during final design checking.

-- LVS START : --
Total area error in layer 0 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 1 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 2 is 0. Elapsed = 0:00:00, CPU = 0:00:00
ERROR : area [(76.630,6.335), (76.830,6.535)] 0.0400 um sqr.
ERROR : area [(0.000,10.845), (0.200,11.045)] 0.0400 um sqr.
ERROR : area [(76.630,10.845), (76.830,11.045)] 0.0400 um sqr.
ERROR : area [(76.630,14.945), (76.830,15.145)] 0.0400 um sqr.
ERROR : area [(76.630,19.045), (76.830,19.245)] 0.0400 um sqr.
ERROR : area [(76.630,23.145), (76.830,23.345)] 0.0400 um sqr.
ERROR : area [(76.630,27.655), (76.830,27.855)] 0.0400 um sqr.
ERROR : area [(76.630,31.755), (76.830,31.955)] 0.0400 um sqr.
ERROR : area [(76.630,35.855), (76.830,36.055)] 0.0400 um sqr.
Total area error in layer 3 is 9. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 4 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 5 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 6 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 7 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 8 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 9 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 10 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 11 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 12 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 13 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 14 is 0. Elapsed = 0:00:00, CPU = 0:00:00
Total area error in layer 15 is 0. Elapsed = 0:00:00, CPU = 0:00:00
ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net.

** Total Floating ports are 1.
** Total Floating Nets are 0.
** Total SHORT Nets are 0.
ERROR : Logical Net VSS is open.
Node 342 is in the region ((2,2),(76,73)).
Node 339 is in the region ((5,69),(71,71)).
Node 341 is in the region ((5,5),(67,5)).
Total seperated nodes are 3.
Potential connection region ((4, 4), (68, 70)).
** Total OPEN Nets are 1.
** Total Electrical Equivalent Error are 0.
** Total Must Joint Error are 0.
 

ThisIsNotSam

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Hi, do anyone know how to solve the open nets ( Logical Net VSS is open) error?

I obtained the error message attached below in LVS during final design checking.
The report says "Total Floating ports are 1." Is this port VSS itself?
It also says "ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net." This is potentially a bigger problem.
 

Brina9797

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The report says "Total Floating ports are 1." Is this port VSS itself?
It also says "ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net." This is potentially a bigger problem.
Hi, thanks for the reply.

I had managed solved the open nets error.

However the message: " Total Floating ports are 1 and ERROR : OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net. " is still shown in the LVS report.

The floating ports is pointing to the error (" OUTPUT PortInst h3/c2/presentstate_reg[0] QN doesn't connect to any net. ")

May I know how to solve this problem?
 

ThisIsNotSam

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you have to understand why this pin is unconnected. It might be possible this is from a flop with Q and QN outputs, so it is fine if one of them is disconnected.
 

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