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Synopsys DesignWare Problem

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phutruan

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Dear everyone,

I'm trying to implement a 1056-bit adder and 374-bit adder. Both adders are implemented using carry look ahead design provided by Synopsys DesignWare.
It is expected that the delay of a 1056-bit adder should be greater than the delay of a 374-bit adder. However, report_timing command reported the contrast result.

Any one have any idea what is happening ? Many thanks in advance
 

phutruan said:
However, report_timing command reported the contrast result.
Any one have any idea what is happening ? Many thanks in advance
Click to expand...

Perhaps you should provide more info, including the results of the timing analysis for both adders.
 

dpaul said:
Perhaps you should provide more info, including the results of the timing analysis for both adders.
Click to expand...

Hi dpaul,

Here is the timing report of 1056-bit adder:
Code: 
Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : add1056_dw
Version: J-2014.09
Date   : Tue Apr  5 00:20:15 2016
****************************************

Operating Conditions: tt40_0.95V_25C   Library: CMOS045_SC_9HD_CORE_LL
Wire Load Model Mode: enclosed

  Startpoint: in2[0] (input port)
  Endpoint: sum[1055] (output port)
  Path Group: (none)
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  add1056_dw         area_7Kto8K           CMOS045_SC_9HD_CORE_LL
  add1056_dw_DW01_add_0
                     area_7Kto8K           CMOS045_SC_9HD_CORE_LL

  Point                                                   Incr       Path
  --------------------------------------------------------------------------
  input external delay                                    0.00       0.00 r
  in2[0] (in)                                             0.00       0.00 r
  U1056/B[0] (add1056_dw_DW01_add_0)                      0.00       0.00 r
  U1056/U6449/Z (HD45_LLA_NAND2X2)                        0.06       0.06 f
  U1056/U6446/Z (HD45_LL_CBI4I6X2)                        0.12       0.17 r
  U1056/U6442/Z (HD45_LL_CBI4I6X2)                        0.09       0.27 f
  U1056/U6425/Z (HD45_LL_CBI4I6X2)                        0.11       0.37 r
  U1056/U6416/Z (HD45_LL_CBI4I6X2)                        0.08       0.46 f
  U1056/U6413/Z (HD45_LL_CBI4I6X2)                        0.10       0.55 r
  U1056/U6409/Z (HD45_LL_CBI4I6X2)                        0.09       0.64 f
  U1056/U6340/Z (HD45_LL_CB4I6X3)                         0.13       0.78 f
  U1056/U6308/Z (HD45_LL_CBI4I1X2)                        0.08       0.86 r
  U1056/U6307/Z (HD45_LL_CBI4I6X2)                        0.08       0.94 f
  U1056/U6030/Z (HD45_LL_CBI4I6X2)                        0.11       1.04 r
  U1056/U5895/Z (HD45_LL_CBI4I6X2)                        0.08       1.12 f
  U1056/U5847/Z (HD45_LL_AOI12X3)                         0.06       1.18 r
  U1056/U5773/Z (HD45_LL_CBI4I6X2)                        0.07       1.25 f
  U1056/U5772/Z (HD45_LL_NOR4ABX2)                        0.08       1.32 r
  U1056/U5747/Z (HD45_LL_AOI112X2)                        0.06       1.39 f
  U1056/U5745/Z (HD45_LL_OAI12X3)                         0.13       1.52 r
  U1056/U5744/Z (HD45_LL_NAND3ABX4)                       0.09       1.61 f
  U1056/U2/Z (HD45_LL_CBI4I6X2)                           0.10       1.72 r
  U1056/U5287/Z (HD45_LL_CBI4I6X2)                        0.08       1.80 f
  U1056/U5238/Z (HD45_LL_CBI4I6X2)                        0.10       1.90 r
  U1056/U5194/Z (HD45_LL_AOI311X2)                        0.09       1.99 f
  U1056/U5192/Z (HD45_LL_OAI12X3)                         0.15       2.14 r
  U1056/U5191/Z (HD45_LL_NAND3ABX4)                       0.09       2.23 f
  U1056/U4/Z (HD45_LL_CBI4I6X2)                           0.10       2.33 r
  U1056/U4734/Z (HD45_LL_CBI4I6X2)                        0.08       2.41 f
  U1056/U4685/Z (HD45_LL_CBI4I6X2)                        0.10       2.51 r
  U1056/U4641/Z (HD45_LL_AOI311X2)                        0.09       2.61 f
  U1056/U4639/Z (HD45_LL_OAI12X3)                         0.16       2.77 r
  U1056/U4637/Z (HD45_LL_NOR4ABX2)                        0.17       2.94 r
  U1056/U4636/Z (HD45_LL_CBI4I6X2)                        0.06       3.00 f
  U1056/U4588/Z (HD45_LL_AOI12X3)                         0.06       3.06 r
  U1056/U4514/Z (HD45_LL_CBI4I6X2)                        0.07       3.12 f
  U1056/U4513/Z (HD45_LL_NOR4ABX2)                        0.08       3.20 r
  U1056/U4488/Z (HD45_LL_AOI112X2)                        0.06       3.27 f
  U1056/U4486/Z (HD45_LL_OAI12X3)                         0.10       3.36 r
  U1056/U4485/Z (HD45_LL_NAND4ABX2)                       0.12       3.49 f
  U1056/U3/Z (HD45_LL_AOI21X3)                            0.11       3.59 r
  U1056/U4467/Z (HD45_LL_CBI4I6X2)                        0.07       3.66 f
  U1056/U4464/Z (HD45_LL_CBI4I6X2)                        0.10       3.76 r
  U1056/U4460/Z (HD45_LL_CBI4I6X2)                        0.08       3.84 f
  U1056/U4458/Z (HD45_LL_OAI12X3)                         0.10       3.93 r
  U1056/U4457/Z (HD45_LL_NAND4ABX2)                       0.12       4.06 f
  U1056/U4275/Z (HD45_LLA_NAND2X2)                        0.10       4.16 r
  U1056/U23/Z (HD45_LL_IVX5)                              0.06       4.22 f
  U1056/U4264/Z (HD45_LL_OAI12X3)                         0.08       4.29 r
  U1056/U4248/Z (HD45_LL_AOI12X3)                         0.09       4.38 f
  U1056/U4246/Z (HD45_LL_OA12X3)                          0.11       4.49 f
  U1056/U4242/Z (HD45_LL_OAI12X3)                         0.08       4.58 r
  U1056/U4240/Z (HD45_LL_AOI12X3)                         0.07       4.65 f
  U1056/U4238/Z (HD45_LLS_XNOR2X3)                        0.07       4.72 f
  U1056/SUM[1055] (add1056_dw_DW01_add_0)                 0.00       4.72 f
  sum[1055] (out)                                         0.00       4.72 f
  data arrival time                                                  4.72
  --------------------------------------------------------------------------
  (Path is unconstrained)


1
And here is the timing report of 374-bit adder
Code: 
Information: Updating design information... (UID-85)
 
****************************************
Report : timing
        -path full
        -delay max
        -max_paths 1
Design : add374_dw
Version: J-2014.09
Date   : Mon Apr  4 01:44:24 2016
****************************************

Operating Conditions: tt40_0.95V_25C   Library: CMOS045_SC_9HD_CORE_LL
Wire Load Model Mode: enclosed

  Startpoint: in2[0] (input port)
  Endpoint: cout (output port)
  Path Group: (none)
  Path Type: max

  Des/Clust/Port     Wire Load Model       Library
  ------------------------------------------------
  add374_dw          area_2Kto3K           CMOS045_SC_9HD_CORE_LL
  add374_dw_DW01_add_0
                     area_2Kto3K           CMOS045_SC_9HD_CORE_LL

  Point                                    Incr       Path
  -----------------------------------------------------------
  input external delay                     0.00       0.00 r
  in2[0] (in)                              0.00       0.00 r
  U374/B[0] (add374_dw_DW01_add_0)         0.00       0.00 r
  U374/U2407/Z (HD45_LLA_NAND2X2)          0.05       0.05 f
  U374/U2404/Z (HD45_LL_CBI4I6X2)          0.11       0.17 r
  U374/U2400/Z (HD45_LL_CBI4I6X2)          0.09       0.26 f
  U374/U2383/Z (HD45_LL_CBI4I6X2)          0.10       0.36 r
  U374/U2374/Z (HD45_LL_CBI4I6X2)          0.08       0.44 f
  U374/U2371/Z (HD45_LL_CBI4I6X2)          0.09       0.54 r
  U374/U2367/Z (HD45_LL_CBI4I6X2)          0.09       0.63 f
  U374/U2298/Z (HD45_LL_CB4I6X3)           0.13       0.76 f
  U374/U2266/Z (HD45_LL_CBI4I1X2)          0.08       0.84 r
  U374/U2265/Z (HD45_LL_CBI4I6X2)          0.07       0.91 f
  U374/U2152/Z (HD45_LL_OA212X5)           0.12       1.04 f
  U374/U1939/Z (HD45_LL_CBI4I6X2)          0.09       1.12 r
  U374/U1865/Z (HD45_LL_CBI4I6X2)          0.08       1.20 f
  U374/U1817/Z (HD45_LL_CBI4I6X2)          0.10       1.30 r
  U374/U1813/Z (HD45_LL_NAND4ABX2)         0.08       1.38 f
  U374/U1810/Z (HD45_LL_CBI4I1X2)          0.17       1.55 r
  U374/U1809/Z (HD45_LL_NAND3ABX4)         0.09       1.64 f
  U374/U1777/Z (HD45_LL_OA31X5)            0.13       1.78 f
  U374/U1773/Z (HD45_LL_CBI4I6X2)          0.09       1.86 r
  U374/U1770/Z (HD45_LL_CBI4I6X2)          0.12       1.98 f
  U374/U1763/Z (HD45_LL_NAND3ABX4)         0.12       2.10 f
  U374/U1731/Z (HD45_LL_OAI13X3)           0.08       2.19 r
  U374/U1727/Z (HD45_LL_CBI4I1X2)          0.10       2.29 f
  U374/U1724/Z (HD45_LL_CB4I1X5)           0.14       2.42 f
  U374/U1717/Z (HD45_LL_NAND3ABX4)         0.10       2.52 f
  U374/U1685/Z (HD45_LL_OAI13X3)           0.08       2.61 r
  U374/U1681/Z (HD45_LL_CBI4I1X2)          0.10       2.71 f
  U374/U1678/Z (HD45_LL_CB4I1X5)           0.14       2.84 f
  U374/U1671/Z (HD45_LL_NAND3ABX4)         0.10       2.94 f
  U374/U1639/Z (HD45_LL_OAI13X3)           0.08       3.03 r
  U374/U1635/Z (HD45_LL_CBI4I1X2)          0.10       3.13 f
  U374/U1632/Z (HD45_LL_CB4I1X5)           0.13       3.26 f
  U374/U1629/Z (HD45_LL_NAND4ABX2)         0.14       3.39 f
  U374/U1622/Z (HD45_LL_OA212X5)           0.13       3.52 f
  U374/U1609/Z (HD45_LL_CBI4I6X2)          0.09       3.61 r
  U374/U1605/Z (HD45_LL_CBI4I6X2)          0.08       3.68 f
  U374/U1602/Z (HD45_LL_CBI4I6X2)          0.09       3.78 r
  U374/U1601/Z (HD45_LL_NOR2AX3)           0.07       3.85 f
  U374/U1596/Z (HD45_LL_NAND4ABX2)         0.14       3.99 f
  U374/U2/Z (HD45_LL_AOI21X3)              0.10       4.09 r
  U374/U1578/Z (HD45_LL_CBI4I6X2)          0.07       4.16 f
  U374/U1575/Z (HD45_LL_CBI4I6X2)          0.10       4.25 r
  U374/U1571/Z (HD45_LL_CBI4I6X2)          0.08       4.33 f
  U374/U1569/Z (HD45_LL_OAI12X3)           0.09       4.42 r
  U374/U1568/Z (HD45_LL_NAND4ABX2)         0.12       4.54 f
  U374/U3/Z (HD45_LL_AOI21X3)              0.10       4.64 r
  U374/U1550/Z (HD45_LL_CBI4I6X2)          0.07       4.71 f
  U374/U1547/Z (HD45_LL_CBI4I6X2)          0.10       4.81 r
  U374/U1543/Z (HD45_LL_CBI4I6X2)          0.07       4.88 f
  U374/U1541/Z (HD45_LL_OA12X3)            0.09       4.97 f
  U374/U1538/Z (HD45_LL_OA12X3)            0.10       5.08 f
  U374/U1536/Z (HD45_LL_OAI12X3)           0.08       5.15 r
  U374/U1534/Z (HD45_LL_AOI12X3)           0.08       5.23 f
  U374/U1532/Z (HD45_LL_OAI12X3)           0.10       5.34 r
  U374/U1531/Z (HD45_LL_AND2X3)            0.11       5.44 r
  U374/U1530/Z (HD45_LL_CB4I6X3)           0.11       5.55 r
  U374/U420/Z (HD45_LL_OR2X5)              0.08       5.63 r
  U374/U419/Z (HD45_LL_AO22X9)             0.06       5.69 r
  U374/CO (add374_dw_DW01_add_0)           0.00       5.69 r
  cout (out)                               0.00       5.69 r
  data arrival time                                   5.69
  -----------------------------------------------------------
  (Path is unconstrained)


1
You can see that the delay of 374-bit adder is greater than 1056-bit adder, which is quite illogical
Both adders are implemented by DesignWare using the same script. The verilog source code of the 374-bit adder is shown below (the verilog code of 1056 is the same but with different bitwidth)
Code Verilog - [expand]
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module add374_dw (
    in1,
    in2,
    cin,
    sum,
    cout
    );
    
    parameter word_length = 374;
 
    input [word_length-1:0] in1, in2;
    input cin;
    output [word_length-1:0] sum;
    output cout;
 
    // synopsys dc_script_begin
    // set_implementation cla U374
    // synopsys dc_script_end
    // instantiate DW01_add
    DW01_add #(word_length) U374(.A(in1), .B(in2), .CI(cin), .SUM(sum), .CO(cout));
 
endmodule
 
Last edited by a moderator:

Hello,

For the 1056-adder you have shown:
Code: 
 sum[1055] (out)                                         0.00       4.72 f
  data arrival time                                                  4.72

For the 374-bit adder you have shown:
Code: 
cout (out)                               0.00       5.69 r
  data arrival time                                   5.69

From the acronyms, it seems like the "sum" denotes the summation of the complete addition process and the other "cout" seems to be the carry-out. Are you comparing the carry-out value of the 374-bit adder to the summation value of the 1056-bit adder?

The sum of 1056-bit adder has to be compared with the sum of 374-bit adder and so is the case for the carry-out. You cannot compare apples with oranges!
 
Last edited:
dpaul said:
Hello,

For the 1056-adder you have shown:
Code: 
 sum[1055] (out)                                         0.00       4.72 f
  data arrival time                                                  4.72

For the 374-bit adder you have shown:
Code: 
cout (out)                               0.00       5.69 r
  data arrival time                                   5.69

From the acronyms, it seems like the "sum" denotes the summation of the complete addition process and the other "cout" seems to be the carry-out. Are you comparing the carry-out value of the 374-bit adder to the summation value of the 1056-bit adder?
Then it is wrong. You cannot compare apples with oranges!
Click to expand...

Hi dpaul,

After synthesizing two adders, I used "report_timing -delay_type max" to get the critical path delay of two adders. It is strange to me why the critical path delay of the 374-bit adder is greater than the 1056-bit adder.
 

Are you synth the two designs (your adders) separately or both of them in a top-level module?

If separately, and assuming that you have run the cmd "report_timing -delay_type max" for each of the designs, Synopsys DC has reported what it has to report.
For the 1056-bit adder, the critical path with the largest delay is the 'sum' output.
For the 374-bit adder, the critical path with the largest delay is the 'cout' output.

From your #1,
It is expected that the delay of a 1056-bit adder should be greater than the delay of a 374-bit adder.
Click to expand...
Yes, true, so you should be comparing sum to sum & cout to cout (not sum against cout).

Check the values of the o/p "sum" for 1056-bit adder & 374-bit adder.
Check the values of the o/p "cout" for 1056-bit adder & 374-bit adder.
 

Hi dpaul,

- Yes two design are synthesized separately.
- Adder is a combo circuit, so its delay should be the delay of the critical path.
- I did compared the value of "cout" for 1056-bit adder and 374-bit adder. It is illogical that the delay for "cout" of 374-bitadder is greater than "cout" of 1056-bit adder, though both are carry look ahead
 

phutruan said:
- I did compared the value of "cout" for 1056-bit adder and 374-bit adder. It is illogical that the delay for "cout" of 374-bitadder is greater than "cout" of 1056-bit adder, though both are carry look ahead
Click to expand...

But what you have posted in #3 doesn't pertain to your claim! There you have posted just the critical paths for both adders.
 

dpaul said:
But what you have posted in #3 doesn't pertain to your claim! There you have posted just the critical paths for both adders.
Click to expand...

Hi dpaul,

I mean I have followed your suggestion to compare the value of "cout" for 1056-bit adder and 374-bit adder.
What I got is that the delay for "cout" of 374-bit adder is greater than "cout" of 1056-bit adder.
 

What I got is that the delay for "cout" of 374-bit adder is greater than "cout" of 1056-bit adder.
Click to expand...
It shouldn't be so for a Syn DW IP.

Are you sure you are not making any trivial mistake elsewhere?
In order to proceed further, I think you have post the design files, compilation log and synthesis log files for any type of analysis.
 

Hello, from your reports, I see that the both paths are unconstrained. It means, the DC did not tried to ptimize these paths. So the critical path delay may be any. Try to add some constaints (like set_max_delay) before synthesis.
 
Hi dpaul,
Here is the script I used
Code: 
##================================================================================================
## Search path settings
##================================================================================================
set DESIGN_LIST [list add1056_dw]
set TOP_DESIGN add1056_dw
set PROCESS_LIB "/net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445"
set search_path [list ./ $PROCESS_LIB/libs ]

##================================================================================================
## Library settings
##================================================================================================
set target_library [list CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db]
set link_library [list * CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db]
set symbol_library [list CMOS045_SC_9HD_CORE_LL.sdb]

##================================================================================================
## Synopsys DesignWare settings
##================================================================================================
set synthetic_library [list dw_foundation.sldb]
set link_library [concat $link_library $target_library $synthetic_library]
set search_path [concat $search_path [list [format “%s%s” $synopsys_root “/dw/sim_ver”]]]
set synlib_wait_for_design_license [list “DesignWare”]

##================================================================================================
## Read all RTL files
##================================================================================================
foreach module "$DESIGN_LIST" {analyze -lib WORK -format verilog ./rtl/$module.v}

##================================================================================================
## Elaborate on top module
##================================================================================================
elaborate $TOP_DESIGN

##================================================================================================
## Change design to top module
##================================================================================================
current_design $TOP_DESIGN

##================================================================================================
## Uniquify and check the design
##================================================================================================
uniquify
check_design

##================================================================================================
## Generic attribute settings
##================================================================================================
set auto_wire_load_selection true

##================================================================================================
## Design constraints settings
##================================================================================================
#set_driving_cell -lib_cell HD45_LL_BFX9 -pin Z [all_inputs]
#set_max_capacitance 250 [all_output]
#set_max_fanout 16 [all_outputs]
set_max_area 0
#set_dp_smartgen_options -optimize_for area
ungroup -flatten -all

##================================================================================================
## Synthesize the design
##================================================================================================
compile -map_effort high

##================================================================================================
## Write out the netlist and some reports
##================================================================================================
#write -format verilog -hierarchy -output ./synthesis_output/$TOP_DESIGN.v
#write_sdc ./synthesis_output/$TOP_DESIGN.sdc
#report_area > ./synthesis_output/$TOP_DESIGN.area
report_timing > ./synthesis_output/$TOP_DESIGN.timing
report_resources

exit

And the synthesis log
Code: 
Design Compiler Graphical
                            DC Ultra (TM)
                             DFTMAX (TM)
                         Power Compiler (TM)
                           DesignWare (R)
                           DC Expert (TM)
                         Design Vision (TM)
                          HDL Compiler (TM)
                         VHDL Compiler (TM)
                            DFT Compiler
                        Library Compiler (TM)
                         Design Compiler(R)

            Version J-2014.09 for RHEL64 -- Aug 25, 2014
               Copyright (c) 1988-2014 Synopsys, Inc.

This software and the associated documentation are confidential and 
proprietary to Synopsys, Inc. Your use or disclosure of this software 
is subject to the terms and conditions of a written license agreement 
between you, or your company, and Synopsys, Inc.

Initializing...
Initializing gui preferences from file  /home/Div6/research/hophdy15/.synopsys_dv_prefs.tcl
##================================================================================================
## Search path settings
##================================================================================================
set DESIGN_LIST [list add1056_dw]
add1056_dw
set TOP_DESIGN add1056_dw
add1056_dw
set PROCESS_LIB "/net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445"
/net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445
set search_path [list ./ $PROCESS_LIB/libs ]
./ /net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445/libs
##================================================================================================
## Library settings
##================================================================================================
set target_library [list CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db]
CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db
set link_library [list * CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db]
* CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db
set symbol_library [list CMOS045_SC_9HD_CORE_LL.sdb]
CMOS045_SC_9HD_CORE_LL.sdb
##================================================================================================
## Synopsys DesignWare settings
##================================================================================================
set synthetic_library [list dw_foundation.sldb]
dw_foundation.sldb
set link_library [concat $link_library $target_library $synthetic_library]
* CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db dw_foundation.sldb
set search_path [concat $search_path [list [format “%s%s” $synopsys_root “/dw/sim_ver”]]]
./ /net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445/libs “/net/numnum/silo3/synopsys/vJ-2014/syn_vJ-2014.09“/dw/sim_ver””
set synlib_wait_for_design_license [list “DesignWare”]
“DesignWare”
##================================================================================================
## Read all RTL files
##================================================================================================
foreach module "$DESIGN_LIST" {analyze -lib WORK -format verilog ./rtl/$module.v}
Running PRESTO HDLC
Compiling source file ./rtl/add1056_dw.v
Presto compilation completed successfully.
Loading db file '/net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445/libs/CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db'
Loading db file '/net/numnum/silo3/synopsys/vJ-2014/syn_vJ-2014.09/libraries/syn/dw_foundation.sldb'
##================================================================================================
## Elaborate on top module
##================================================================================================
elaborate $TOP_DESIGN
Loading db file '/net/numnum/silo3/synopsys/vJ-2014/syn_vJ-2014.09/libraries/syn/gtech.db'
Loading db file '/net/numnum/silo3/synopsys/vJ-2014/syn_vJ-2014.09/libraries/syn/standard.sldb'
  Loading link library 'CMOS045_SC_9HD_CORE_LL'
  Loading link library 'gtech'
Running PRESTO HDLC
Presto compilation completed successfully.
Elaborated 1 design.
Current design is now 'add1056_dw'.
1
##================================================================================================
## Change design to top module
##================================================================================================
current_design $TOP_DESIGN
Current design is 'add1056_dw'.
{add1056_dw}
##================================================================================================
## Uniquify and check the design
##================================================================================================
uniquify
1
check_design
1
##================================================================================================
## Generic attribute settings
##================================================================================================
set auto_wire_load_selection true
true
##================================================================================================
## Design constraints settings
##================================================================================================
#set_driving_cell -lib_cell HD45_LL_BFX9 -pin Z [all_inputs]
#set_max_capacitance 250 [all_output]
#set_max_fanout 16 [all_outputs]
set_max_area 0
1
#set_dp_smartgen_options -optimize_for area
ungroup -flatten -all
Warning: Design has no hierarchy.  No cells can be ungrouped. (UID-228)
0
##================================================================================================
## Synthesize the design
##================================================================================================
compile -map_effort high
Information: Evaluating DesignWare library utilization. (UISN-27)

============================================================================
| DesignWare Building Block Library  |         Version         | Available |
============================================================================
| Basic DW Building Blocks           | J-2014.09-DWBB_201409.0 |     *     |
| Licensed DW Building Blocks        | J-2014.09-DWBB_201409.0 |           |
============================================================================



  Beginning Pass 1 Mapping
  ------------------------
  Processing 'add1056_dw'

  Updating timing information
Information: Updating design information... (UID-85)

  Beginning Implementation Selection
  ----------------------------------
  Processing 'add1056_dw_DW01_add_0'

  Beginning Mapping Optimizations  (High effort)
  -------------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:07    7397.1      0.00       0.0       0.0                          
    0:00:07    7397.1      0.00       0.0       0.0                          
    0:00:07    7397.1      0.00       0.0       0.0                          
    0:00:07    7397.1      0.00       0.0       0.0                          
    0:00:07    7397.1      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          



  Beginning Delay Optimization Phase
  ----------------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          


  Beginning Area-Recovery Phase  (max_area 0)
  -----------------------------

                                  TOTAL                                      
   ELAPSED            WORST NEG   SETUP    DESIGN                            
    TIME      AREA      SLACK     COST    RULE COST         ENDPOINT         
  --------- --------- --------- --------- --------- -------------------------
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:07    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:08    7110.9      0.00       0.0       0.0                          
    0:00:12    7110.2      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
    0:00:12    7109.5      0.00       0.0       0.0                          
Loading db file '/net/vlsiserver/usr1/library/STM/cmos040lp_23/CMOS045_SC_9HD_CORE_LL_C40LP_SNPS-AVT-CDS@2.1.UD7445/libs/CMOS045_SC_9HD_CORE_LL_tt40_0.95V_25C.db'

  Optimization Complete
  ---------------------
1
##================================================================================================
## Write out the netlist and some reports
##================================================================================================
#write -format verilog -hierarchy -output ./synthesis_output/$TOP_DESIGN.v
#write_sdc ./synthesis_output/$TOP_DESIGN.sdc
#report_area > ./synthesis_output/$TOP_DESIGN.area
report_timing > ./synthesis_output/$TOP_DESIGN.timing
report_resources
 
****************************************
Report : resources
Design : add1056_dw
Version: J-2014.09
Date   : Tue Apr  5 23:30:51 2016
****************************************

Resource Sharing Report for design add1056_dw

===============================================================================
|          |              |            | Contained     |                      |
| Resource | Module       | Parameters | Resources     | Contained Operations |
===============================================================================
| r59      | DW01_add     | width=1056 |               | U1056                |
===============================================================================


Implementation Report
===============================================================================
|                    |                  | Current            | Set            |
| Cell               | Module           | Implementation     | Implementation |
===============================================================================
| U1056              | DW01_add         | cla                | cla            |
===============================================================================

1
exit

Thank you...

- - - Updated - - -

oratie said:
Hello, from your reports, I see that the both paths are unconstrained. It means, the DC did not tried to ptimize these paths. So the critical path delay may be any. Try to add some constaints (like set_max_delay) before synthesis.
Click to expand...

Hi oratie,
You are correct. I used "set_max_delay 0" to force the tool to make the delay of each adder as small as possible. Now the delay of 374-bit adder is smaller than the delay of 1056-bit adder
 

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