sudeep_
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Hi,
i would like to get the low standard cell size for basic inverter, but am getting little higher.
How do i reduce the standard cell size(Trnasistor size up to Pmos -0.5uW/0.65)?
also our software has no these Maximum (and minimum) capacitance, Cell degradation in Design Rule Constraints.
Thanks in advance.
i would like to get the low standard cell size for basic inverter, but am getting little higher.
How do i reduce the standard cell size(Trnasistor size up to Pmos -0.5uW/0.65)?
also our software has no these Maximum (and minimum) capacitance, Cell degradation in Design Rule Constraints.
Thanks in advance.