Synopsys Design Compiler

[Aggieland]

In His Name
HI
I am trying to retime my pipelined data path.
My problem is after retiming I need the power consumption of each pipeline stage separately.
Is there any way that I can find the power consumption of each stage automatically?

Please Help me.
Regards;

 

[lostinxlation]

But why do you want to measure the power on the particular stage ?
While one instruction is running in one of the stages, other instructions are running in the other stages at the same time and all consumes the power. I don't see the point to look at the power within a single stage when you are running it in pipeline.

 

[Aggieland]

The problem is I used clock gating and I may disable one stage while there is no data for it. So, in that case the power consumption will be less. I need to know the power of each pipeline stage to calculate the power saved with clock gating

 

[lostinxlation]

but if there is data, you can't disable the clock, can you ? That's the worst case scenario and if you measure the clock with disabled clock, which may or may not happen in real operation, the power number would be too optimistic.

Anyway, run simulation with vcd and in that way, you can control the data if you want to disable or enable the clocks.

 

[Aggieland]

But How can I measure the power consumption of each pipeline stage?

 

[lostinxlation]

it's a typical power analysis flow with .vcd and simulator. I can bet you won't be able to specify the pipe stage that you measure the power for since no one does such a method to measure the power, but you can control the data in .vcd which consequently can disable the other pipe stage that you aren't interested in.

 

[Aggieland]

It was helpful.
Thanks

 

[Adam.Yakuvitz]

We implemented a new flow within our company to use Cadence NC-Sim/IES with something called Power Profiling. Along with dynamic simulation, you can also do power simulation and "watch" the power usage across pipeline stages. However, reporting average power is not possible, but if I understand correctly, your goal may to measure out the high power sections and balance it across the pipe stages, which you will be able to do through this Power Profiling flow or application.

Talk to you Cadence AE and they will be able to demonstrate power profiling with IES. One of their AE's in Asia set us up with this flow for us.

-- adam

 

[Aggieland]

We have the top level simulator that tells us exactly when a stage is clock gated and we are trying to calculate the power using design compiler. We have the RTL code for our design. I know that using .vcd the power estimation will be more accurate but we try to calculate power of each pipeline stage after introducing pipeline. In This scenario the design compiler is using probability of 0.5 for each signal to be "0" or "1".

 

[lostinxlation]

OK, if I were you, I'd do this.

All the cell has power arc in the library and I'd find a way to get power consumption from each of all the cells that belong to the pipeline I'm interested in, while running simulation.

First, writing a script(DC, perl, python.... whatever works) to extract all the instances between certain flops.
Second, getting transition times and caps on all the nets belonging to the given pipe stage and looking up the power arc to get the power from each cells you extracted and sum them up every cycle. That's a power consumption only from the certain pipe stage.

I'd think there should be a command to get a power number for an individual instance. If it doesn't have one, I'd write a script to get transition times and cap on all the nets in the give pipe stage and consult with power arc in the lib to get a power number.. And repeat this for all the instances and sum them up..

 

[Aggieland]

We came with this Idea. We can Apply the clock gating to our registers and after retiming (or may be before retiming) we can disable all the registers of all stages but one stage. In this way the power consumption of all registers of the stages and combinational logic after that will be zero do to no transition in the signals, in that way only one stage will consume the power. do you think it is a valid way? Also, If there is a way or instruction that can calculate the power of each stage without doing this can anybody help me find it?