Synopsys design compiler error problem

[minho_ha]

Hi, i got a error message below using synopsys dc.

Error: /home/junki.park/project/DIGITAL/design/mem_test_v3/source/accurate_multiplier.v:27: The width of port p4 on instance stage1_comp5 of design ACC_COMP is inconsistent with other instantiations of the same design. (ELAB-369)
Error: Cannot resolve pin p4[31] on cell ACC_COMP:stage1_comp5. (ELAB-327)
Error: Can't read 'verilog' file '/home/junki.park/project/DIGITAL/design/mem_test_v3/source/accurate_multiplier.v'. (UID-59)
No designs were read

And here is my verilog code.

`timescale 1ns / 1ps

module accurate_multiplier(a,b,out);
    input [7:0] a;
    input [7:0] b;
    output [15:0] out;

    wire [1:0] ha1_sum, ha1_cout;
    wire [7:0] comp1_carry, comp1_cout, comp1_sum;
    wire [1:0] fa1_sum, fa1_cout;
    
    wire ha2_sum, ha2_cout;
    wire [9:0] comp2_carry, comp2_cout, comp2_sum;
    wire fa2_sum, fa2_cout;
    
    wire [1:0] ha3_sum, ha3_cout;
    wire [11:0] fa3_sum, fa3_cout;
    
    // first stage
    HA stage1_ha0(a[4]&b[0],a[3]&b[1],ha1_cout[0],ha1_sum[0]);
    HA stage1_ha1(a[2]&b[4],a[1]&b[5],ha1_cout[1],ha1_sum[1]);
    ACC_COMP stage1_comp0(a[5]&b[0],a[4]&b[1],a[3]&b[2],a[2]&b[3],ha1_cout[0],comp1_cout[0],comp1_carry[0],comp1_sum[0]);
    ACC_COMP stage1_comp1(a[6]&b[0],a[5]&b[1],a[4]&b[2],a[3]&b[3],comp1_cout[0],comp1_cout[1],comp1_carry[1],comp1_sum[1]);
    ACC_COMP stage1_comp2(a[7]&b[0],a[6]&b[1],a[5]&b[2],a[4]&b[3],comp1_cout[1],comp1_cout[2],comp1_carry[2],comp1_sum[2]);
    ACC_COMP stage1_comp3(a[3]&b[4],a[2]&b[5],a[1]&b[6],a[0]&b[7],ha1_cout[1],comp1_cout[3],comp1_carry[3],comp1_sum[3]);
    ACC_COMP stage1_comp4(a[7]&b[1],a[6]&b[2],a[5]&b[3],a[4]&b[4],comp1_cout[2],comp1_cout[4],comp1_carry[4],comp1_sum[4]);
    ACC_COMP stage1_comp5(a[3]&b[5],a[2]&b[6],a[1]&b[7],0,comp1_cout[3],comp1_cout[5],comp1_carry[5],comp1_sum[5]);
    ACC_COMP stage1_comp6(a[7]&b[2],a[6]&b[3],a[5]&b[4],a[4]&b[5],comp1_cout[4],comp1_cout[6],comp1_carry[6],comp1_sum[6]);
    ACC_COMP stage1_comp7(a[7]&b[3],a[6]&b[4],a[5]&b[5],a[4]&b[6],comp1_cout[6],comp1_cout[7],comp1_carry[7],comp1_sum[7]);
    FA stage1_fa0(a[3]&b[6],a[2]&b[7],comp1_cout[5],fa1_cout[0],fa1_sum[0]);
    FA stage1_fa1(a[7]&b[4],a[6]&b[5],comp1_cout[7],fa1_cout[1],fa1_sum[1]);
    
    // second stage
    HA stage2_ha0(a[2]&b[0],a[1]&b[1],ha2_cout,ha2_sum);
    ACC_COMP stage2_comp0(a[3]&b[0],a[2]&b[1],a[1]&b[2],a[0]&b[3],ha2_cout,comp2_cout[0],comp2_carry[0],comp2_sum[0]);
    ACC_COMP stage2_comp1(ha1_sum[0],a[2]&b[2],a[1]&b[3],a[0]&b[4],comp2_cout[0],comp2_cout[1],comp2_carry[1],comp2_sum[1]);
    ACC_COMP stage2_comp2(comp1_sum[0],a[1]&b[4],a[0]&b[5],0,comp2_cout[1],comp2_cout[2],comp2_carry[2],comp2_sum[2]);
    ACC_COMP stage2_comp3(comp1_sum[1],ha1_sum[1],a[0]&b[6],comp1_carry[0],comp2_cout[2],comp2_cout[3],comp2_carry[3],comp2_sum[3]);
    ACC_COMP stage2_comp4(comp1_sum[2],comp1_carry[1],comp1_sum[3],0,comp2_cout[3],comp2_cout[4],comp2_carry[4],comp2_sum[4]);
    ACC_COMP stage2_comp5(comp1_sum[4],comp1_carry[2],comp1_sum[5],comp1_carry[3],comp2_cout[4],comp2_cout[5],comp2_carry[5],comp2_sum[5]);
    ACC_COMP stage2_comp6(comp1_sum[6],comp1_carry[4],comp1_carry[5],fa1_sum[0],comp2_cout[5],comp2_cout[6],comp2_carry[6],comp2_sum[6]);
    ACC_COMP stage2_comp7(comp1_sum[7],comp1_carry[6],fa1_cout[0],a[3]&b[7],comp2_cout[6],comp2_cout[7],comp2_carry[7],comp2_sum[7]);
    ACC_COMP stage2_comp8(fa1_sum[1],comp1_carry[7],a[5]&b[6],a[4]&b[7],comp2_cout[7],comp2_cout[8],comp2_carry[8],comp2_sum[8]);
    ACC_COMP stage2_comp9(a[7]&b[5],a[6]&b[6],a[5]&b[7],fa1_cout[1],comp2_cout[8],comp2_cout[9],comp2_carry[9],comp2_sum[9]);
    FA stage2_fa0(a[7]&b[6],a[6]&b[7],comp2_cout[9],fa2_cout,fa2_sum);
    
    // third stage
    HA stage3_ha0(a[1]&b[0],a[0]&b[1],ha3_cout[0],ha3_sum[0]);
    FA stage3_fa0(ha2_sum,a[0]&b[2],ha3_cout[0],fa3_cout[0],fa3_sum[0]);
    HA stage3_ha1(comp2_sum[0],fa3_cout[0],ha3_cout[1],ha3_sum[1]);
    FA stage3_fa1(comp2_sum[1],comp2_carry[0],ha3_cout[1],fa3_cout[1],fa3_sum[1]);
    FA stage3_fa2(comp2_sum[2],comp2_carry[1],fa3_cout[1],fa3_cout[2],fa3_sum[2]);
    FA stage3_fa3(comp2_sum[3],comp2_carry[2],fa3_cout[2],fa3_cout[3],fa3_sum[3]);
    FA stage3_fa4(comp2_sum[4],comp2_carry[3],fa3_cout[3],fa3_cout[4],fa3_sum[4]);
    FA stage3_fa5(comp2_sum[5],comp2_carry[4],fa3_cout[4],fa3_cout[5],fa3_sum[5]);
    FA stage3_fa6(comp2_sum[6],comp2_carry[5],fa3_cout[5],fa3_cout[6],fa3_sum[6]);
    FA stage3_fa7(comp2_sum[7],comp2_carry[6],fa3_cout[6],fa3_cout[7],fa3_sum[7]);
    FA stage3_fa8(comp2_sum[8],comp2_carry[7],fa3_cout[7],fa3_cout[8],fa3_sum[8]);
    FA stage3_fa9(comp2_sum[9],comp2_carry[8],fa3_cout[8],fa3_cout[9],fa3_sum[9]);
    FA stage3_fa10(fa2_sum,comp2_carry[9],fa3_cout[9],fa3_cout[10],fa3_sum[10]);
    FA stage3_fa11(a[7]&b[7],fa2_cout,fa3_cout[10],fa3_cout[11],fa3_sum[11]);
    
    assign out[0] = a[0]&b[0];
    assign out[1] = ha3_sum[0];
    assign out[2] = fa3_sum[0];
    assign out[3] = ha3_sum[1];
    assign out[4] = fa3_sum[1];
    assign out[5] = fa3_sum[2];
    assign out[6] = fa3_sum[3];
    assign out[7] = fa3_sum[4];
    assign out[8] = fa3_sum[5];
    assign out[9] = fa3_sum[6];
    assign out[10] = fa3_sum[7];
    assign out[11] = fa3_sum[8];
    assign out[12] = fa3_sum[9];
    assign out[13] = fa3_sum[10];
    assign out[14] = fa3_sum[11];
    assign out[15] = fa3_cout[11];
        
endmodule

module HA(a,b,cout,sum);

    input a,b;
    output cout, sum;
    
    assign sum = a^b;
    assign cout = a&b;
    
endmodule

module FA(a,b,cin,cout,sum);

    input a,b,cin;
    output cout, sum;
    
    assign sum = a^b^cin;
    assign cout = (a&b)|(b&cin)|(cin&a);
   
 endmodule
 
 module ACC_COMP(x1,x2,x3,x4,cin,cout,carry,sum);
 
    input x1,x2,x3,x4,cin;
    output cout,carry,sum;
    
    assign sum = x1^x2^x3^x4^cin;
    assign carry = ((x1^x2^x3^x4)&cin)|(~(x1^x2^x3^x4)&x4);
    assign cout = ((x1^x2)&x3)|(~(x1^x2)&x1);
     
 endmodule

Using this code, Xilinx Vivado works well without no errors.

But, using Synopsys DC, I got a error message. How can i solve this problem??

 

[slutarius]

"The width of port p4 on instance stage1_comp5 of design ACC_COMP"

Here I can not see which is port p4 on your design.
Did you post the same file with the one in synthesis ?

and Error: Cannot resolve pin p4[31] on cell ACC_COMP:stage1_comp5. (ELAB-327...

Where can we see p4[31] pin on the code ?

 

[minho_ha]

I think p4 means that 4th port of stage_comp5.

Similar codes have similar errors, too. (similar statements like "Error: /home/junki.park/project/DIGITAL/design/mem_test_v3/source/proposed_v2_nonrecovery.v:106: The width of port p5 on instance stage1_acc_comp1 of design ACC_COMP is inconsistent with other instantiations of the same design. (ELAB-369)
Error: Cannot resolve pin p5 on cell ACC_COMP:stage1_acc_comp1. (ELAB-327)")

I heard that Synopsys DC has more tight rules than Xilinx Vivado. So, errors occur.

 

[ThisIsNotSam]

ok, so there is a lot of bad practice going on here, that probably is related to your messages.

let us analyse this line here:

HA stage2_ha0(a[2]&b[0],a[1]&b[1],ha2_cout,ha2_sum);

you have logic being performed at instantiation time. this is poor. instead do something like:

wire condition;
assign condition = a[2]&b[0];
HA stage2_ha0(condition,a[1]&b[1],ha2_cout,ha2_sum);

second thing is your instantiation is order based instead of name based. this is also poor. please change it to something like this:

wire condition;
assign condition = a[2]&b[0];
HA stage2_ha0(
.condition (condition),
.otherport (otherport),
.cout (cout),
.sum(sum)
);

- - - Updated - - -

and the error you are seeing is because 0 is being expanded to 32 bits I believe, whereas the other instances of this submodule have a 1 bit port.