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#### politicante

##### Member level 2
Hi , I'm at the beginning os ASIC design.I would like to know if is there a tutorial on the net teaching how to start with vhdl code and end with chip layout using Synopsys DC,Modelsim and Cadence IC.

Thanks a lot
Politicante

P.S.I know(not very well) how to use single tools,I found hard to make them work together

#### s0shinde

##### Member level 1
go to www.deepchip.com and you can find a tutorial for synopsys DC in the downloads section.
For cadence tutorial just search in google for the product + tutorial you want. If you are using Cadence LDV, the docs directory contains lots of pdf files(which are similar to tutorials) for each product like Verilog-Xl, SignalScanUI, SimVision, SimControl.

#### avin11

##### Newbie level 5
What kind of tips do you need in detail?

#### s0shinde

##### Member level 1
Hi,
(1) First you need to design your system using RTL(Verilog or VHDL). You can take these files in to modelsim and simulate it. For that first open modelsim and create a project and corresponding "work" directory to store your design files. THen you have to write a stimulus file namely stim.do and execute it on the modelsim command prompt. The stimulus file is something like this:
/$design_name/clock 0 0, 0 10, 1 20, 0 30 -r200 /$design_name/A 0 0, 1 5, 0 30
run -200

and so on for all inputs and outputs you want to monitor. Also test your design with Test benches.

(2) If everything works well, take that RTL file to Synopsys DC and compile it with the ASIC technology files supplied by the ASIC foundary Company like LSI logic or Kawasaki LSI etc.
You may also perform Lint checks and DFT checks using Synopsys DFT Compiler. The DC script commands can be found in DC tutorial from www.deepchip.com (downloads).

(3) you can per form static timing analysis using Synopsys Primetime.
(4) Use LBIST for BIST cell and scan chain insertion. Then you can use the Floorplan manager or Avant Jupiter for Floor plan. For place and route, ClockTree Synthesis there is Avant Astro. Use Synopsys Star-RC_XT for parasitic parameter extraction. You will also need to prepare data for the Synopsys Milkyway database.

(5) Once you get timing closure, you will have to take the design to generate the GDSII file which will be used for layout and actual ASIC design by the Foundary.

hitblda

### hitblda

Points: 2

#### standardon

##### Junior Member level 2
I long to study how to laern write vhdl code on fpga
is there a good website!

#### s0shinde

##### Member level 1
Coding in VHDL for FPGA's is very simple. I mean, you don't need to do all the steps in ASIC Design Flow. But if you are starting to learn VHDL, learning Verilog is much easier as it is very much similar to C. For VHDL coding on FPGA, there are books like VHDL Primer, VHDL synthesis primer. First tell me what FPGA simulation and FPGA writing tools are using using. For simulation, there are tools like Modelsim, Cadence NC-VHDL, Synopsys DC. For writing to FPGA, there are tools like FPGA Express, Leonardo Spectrum, Xilinx ISE 5.1, Altera Maxplus - II, Altera Quartus. Symplicity Synpilfy etc.

#### AlexWan

##### Full Member level 5
and I think we have many chances to try it in FPGA, but if we do ASIC, we have the only chance to tape out.

#### melonpy

##### Junior Member level 1
AlexWan said:
and I think we have many chances to try it in FPGA, but if we do ASIC, we have the only chance to tape out.

Yes, if we decide to tapeout one chip, we must ensure the correctness of our design.

#### s0shinde

##### Member level 1
But ASIC designs are much more faster. We can perform various checks and make the final design matching the required timing constraints.

#### bagane

##### Newbie level 4
It is very simple Coding in VHDL for FPGA's .

#### oasis

##### Junior Member level 1
language is just a method, and the key is the circuit itself, such as the system architecture, the algorithm. the description language is changing from low level to high level, but the circuit will not change.

#### s0shinde

##### Member level 1
Hello,
I have a question to ask.
Suppose there are two flipflops in an ASIC design and there is Some combinatorial logic between them. Now there is a setup time violation in the second flipflop. How can we correct this setup time violation? I know of some techniques, can anyone suggest some more. If anyone knows how to do that in Synopsys DC or Primetime, any commands. Also correct me if I am wrong

(1) Modify the combinatorial logic is one way. But suppose it is not possible to reduce to more.
(2) Use of larger sized gates in that combinatorial logic.
(3) Replace the first flipflop with 2 transperant latches connected in Master-Slave mode.
(4) Divide the Combinatorial path in to two and place a flipflop between them.

Are these correct. Any sugestions.

#### edacw1

##### Full Member level 4
I think you can read SOLD for Synopsys and OpenBook for Cadence.

elaheienazeman

### elaheienazeman

Points: 2

#### armer

##### Member level 5
Who can introduce some tips for soc encounter?

#### zzy_zy

##### Junior Member level 2
you can search with "soc" in this forum.

#### haoboy

##### Member level 2
i think,HDL-Chipdesign is a nice book for u.

#### AlexWan

##### Full Member level 5
haoboy said:
i think,HDL-Chipdesign is a nice book for u.

Hi haoboy,

Thanks

#### arunragavan

ummm well.. to know and learn more abt EDA tools.. try this site h**p://demosondemand.com

VHDL programming by examples is a nice book..

Douglas L Perry is the author, Mc Graw Hill publication..

this is a wonderful book.. i have a copy in the ebook format.. might surely help u a lot.

with regards,

#### matthew_wang

##### Member level 3
If you have installed some tools of these two system, you can find lots of documents under their directories, and for each tools, in general ,there are some tutorials about "quick start". In addition, you can refer to some books on ASCI design flow.

#### s_vlsi

##### Junior Member level 2
Hi,
Can anyone tell me abt do file. how to creat it?

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