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Synops. FPGA compiler -> timing constraints problem

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vladr

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Help!

I have just installed FPGA Compiler 3.7.0.7408 (2001.08-FC3.7) and loaded up a vhdl file. Problem is, for almost all technologies (Atmel, Cypress, Lattice, etc.) I don't get any timing information after optimization (estimated clock freq. says "no paths", and all clock<->combinatorial delays are N/A, all clock<->clock delays are 0) and my constraints are generally ignored -- only Altera and Xilinx worked for me. Have I misconfigured something, or is FPGA Compiler lacking timing information for those manufacturers? How can I optimize without timing information?!

I'd use Synplify, except that Synplicty don't support some of the chips I'm particularly interested in (for $$$ reasons).

Please see attachment for comparative outputs between a Xilinx (good) and Cypress (bad) run.

Thanks!

Cheers,
V.
 

kinysh

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I never use the timing of synopsys fpga.

that is rubbish. never tell you anything meaningful.

however synplicity's is much better, if it say it can run 30M, then xilinx can really run about 30Mhz.
 

lipton

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kinysh said:
however synplicity's is much better, if it say it can run 30M, then xilinx can really run about 30Mhz.
That's only true for small devices. On big devices all synthesis tools fail to estimate routing delay correctly.
 

vladr

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lipton said:
kinysh said:
however synplicity's is much better, if it say it can run 30M, then xilinx can really run about 30Mhz.
That's only true for small devices. On big devices all synthesis tools fail to estimate routing delay correctly.
Good, but then how do I know if my design satisfies some timing constraints? If the results were not accurate at least I could have added some sort of uncertainty margin, but with no timing results what can I do? I'm still curious if the lack of timing information for some technologies in FPGA Compiler is due to a mistake on my part/misconfiguration, or if it's due to FPGA Compiler's libraries themselves lacking this information. Aslo, assuming that I use Synplicity, what sorts of error margins should I allow for (10%? 50%?), and/or how can I deduce these margins empirically (without passign ten million test vectors through the FPGA)?

Thanks!
V.
 

lipton

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For devices bigger than Virtex2-1000 error margin is usually 15-20%.
For devices smaller than Virtex2-1000 error margin is usually 5-10%

The only accurate timing report is one done after PAR.
 

kinysh

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lipton said:
For devices bigger than Virtex2-1000 error margin is usually 15-20%.
For devices smaller than Virtex2-1000 error margin is usually 5-10%

The only accurate timing report is one done after PAR.
yes, I agree.
howeve I only use virtexe-1600
 

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