synchronous reset (verilog)

[pwq1999]

verilog counter with synchronous reset

i write synchronous reset as follow:
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit<=1'b0;
else
begin
if(!rtl8305_mtxen)
toggle_bit<=1'b0;
else
toggle_bit<=~toggle_bit;
end
end

but when i view the RTL Schematic, i found that the syn_rst_n signal make the logic or with the !rtl8305_mtxen signal ,which i don't expecte, so anyone can help me out how to express the synchronous reset without adding additional logic in reset input?
thanks in advance!

 

[j_andr]

/.../ found that the syn_rst_n signal make the logic or
with the !rtl8305_mtxen signal/...

this is what you wrote in the rtl;
can you describe the functionality you need ?
--

 

[pwq1999]

i want a multiplexer appear in front of the flip-flop, and the rtl8305_mtxen behaves as the select control signal. actually i don't want any logic appear in the reset input of the flip-flop, as i worry that it may make glitch in the reset input of flip-flop.

 

[research_vlsi]

u can try your code like this

wire out;
always@(posedge sys_clk_25m)
begin
	if(!syn_rst_n)
		toggle_bit<=1'b0;
	else
	   toggle_bit<=out;
	/*if(!rtl8305_mtxen)
		toggle_bit<=1'b0;
	else
		toggle_bit<=~toggle_bit;*/
end 
assign out = rtl8305_mtxen?!toggle_bit:1'b0;

so that u will not get any logic in reset of your flip flop. since u used !syn_rst_n, so inverter will be inferred in synthesis tool..

 

[j_andr]

want a multiplexer appear in front of the flip-flop

in fact a mux is also a set of and/or gates, or - going down
to fpga architecture - it is composed of look-up tables as AND/OR gates are;
mux/or/and - it's just a graphical representation of the rtl;

i worry that it may make glitch in the reset input of flip-flop

you can have the same glitches if a mux is used;
but any glitches, if out of clock active slope, are not danger if they
appear at the input of a flip-flop;
--

 

[pwq1999]

thanks ,j_andr and research_vlsi, you two help me out! now i get the idea!

 

[xihushui]

try this code
always@(posedge sys_clk_25m)
begin
if(!syn_rst_n) begin
toggle_bit<=1'b0;
end
else if(!rtl8305_mtxen) begin
toggle_bit<=1'b0;
end
else begin
toggle_bit<=~toggle_bit;
end
end

 

[pwq1999]

i can not see your code have difference with the code i posted above!

 

[sheik_vb]

try this code

assign reset_n = syn_rst_n & rtl8305_mtxen ;

always@(posedge sys_clk_25m)
begin
if(!reset_n) begin
toggle_bit<=1'b0;
end
else
toggle_bit<=~toggle_bit;
end

 

[kib]

try this code

assign temp = rtl8305_mtxen ? (~toggle_bit) : 1'b0;

always @(posedge sys_clk_25m)
begin
if(!syn_rst_n)
toggle_bit <= 1'b0;
else
begin
toggle_bit <= temp;
end

 

[pwq1999]

thanks you all, i have change the synchronous reset to asynchronous reset, and no logic appear in front of the reset of the flip-flop,but i believe that kib's code works well, and thanks you all again!