synchronous frequency divider design.

[nathanee]

Hi all,

Please help to suggest reference circuit or paper of SYNCHRONOUS frequency divider design, which is 8-bit.

The design should be schmatic entry instead of HDL.

Thanks in advance.

BRs,
-nathan

 

[eda_wiz]

what fequency u want to achieve?

 

[nathanee]

The frequency is used in PLL, thus the frequency range is from 100MHz to 500MHz.

BR,
-nathan

 

[eda_wiz]

I mean to ask... say your input frequency is X. then what is the output frequency interms of X required for the freuency divider .

 

[syncom]

which reference book i can refer?

 

[eda_wiz]

which reference book i can refer?

for what??

 

[AlexWan]

hi,

This a paper named "Clock Dividers Made Easy".
SNUG Boston,2002.