"Trying to synchronize a binary count value from one clock domain to another is problematic because every bit of an
n-bit counter can change simultaneously (example 7->8 in binary numbers is 0111->1000, all bits changed)."
How is that a problem?
Why registering a single bit is OK but a [3:0] vector isn't ?
signal a : unsigned(7 downto 0);
signal b : integer range 0 to 255;
a <= a + 1; --done
if b = 255 then
b <= 0; --because this wont happen in simulation implicitly and it will error otherwise.
else
b <= b + 1;
end if;
/*
The purpose of this function is to convert an unsigned
binary number to reflected binary Gray code.
*/
unsigned short binaryToGray(unsigned short num)
{
return (num>>1) ^ num;
}
unsigned short grayToBinary(unsigned short num)
{
unsigned short temp = num ^ (num>>8);
temp ^= (temp>>4);
temp ^= (temp>>2);
temp ^= (temp>>1);
return temp;
}
as for types, i think integers will always init to 0, instead of 'x'. There may be some sim differences as a result. I'd expect int's to be faster for sim overall. as always, I don't really see why VHDL requires unsigned separate from std_logic_vector -- in this case "unsigned" has been used in the examples, but there isn't any strong reason to use unsigned vs signed. I don't see how calling it "unsigned" is any more descriptive than calling it "std_logic_vector".
it should be "mod 256" - Precision and Synplify get it rightI think most synthesizers will pick up "x <= (x + 1) mod 255;" as the correct operation
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