synchronous clock selector

[buenos]

hi

i want to make a synchronous clock selector.
There are two 33MHz clock signal inputs and a clock output.
there is an asynchronous selector signal coming from a state machine which might be clocked by one of the 2 clock inputs.

so, i need a selector circuit, which makes shure that there will not be pulses shorter than T_clk/2 on the clock output when switching from one source to the other.

This has to be done in a behavioral way, so make it platform independent.

how can it be done in VHDL?

 

[sudhirkv]

You can use a MUX for the selection circuit.

 

[buenos]

that would not guarantee a minimum pulse width

 

[sudhirkv]

Let me make myself clear....
You have a logic which has to run at a clock by default. based on the selection circuit the logic has to run based on the selected clock if am not wrong..

If this is the case i can suggest you one thing.

Use a flag say a register. Once when there is change in the selection reset the flag to 0. then set the flag during the clkout of the mux. have a condition in yor logic that you logic should run only when the flag is 1.

this suggetion will delay the clock by one clock cycle and you will get one full clock to execute the logic

can u please tell me where u r going to apply this

 

[RBB]

You made need to synchronize your select signal to each of the two separate clock domains, such that you have two select signals.
You should then be able to follow the principles shown in this link below...
https://www.design-reuse.com/articles/5827/techniques-to-make-clock-switching-glitch-free.html

 

[sudhirkv]

@RRB
The document was really usefull...
Good show

 

[shitansh]

hi

i want to make a synchronous clock selector.
There are two 33MHz clock signal inputs and a clock output.
there is an asynchronous selector signal coming from a state machine which might be clocked by one of the 2 clock inputs.

so, i need a selector circuit, which makes shure that there will not be pulses shorter than T_clk/2 on the clock output when switching from one source to the other.

This has to be done in a behavioral way, so make it platform independent.

how can it be done in VHDL?

Hi,

see below topics and my reply.







HTH
--
Shitansh Vaghela

 

[buenos]

hi

thanks for everyone.
I will read these through.