Synchronous BRAM simulation problem

[FINALFANTASYFAN]

I have a design using 2 BRAM blocks, one contains filter coef, one contains image. As simulating this design, I encounter a problem. These are single port RAM and the whole design is synchronized on CLK's rising edge.:
- If CLK starts ( initialized value ) by 0 then everything is OK. It gives me the same result as what I've got in MatLab.
- But if I initialize CLK by 1 then BRAM data output sometimes turns into UNKNOWN VALUE when address input changes. Others, it still works OK.

What is the matter with BRAM ( or synchronous RAM ) simulation? Does anyone experience this? Pls help me!

 

[kel8157]

that looks like 1) timing violations somewhere in your design, 2) did you initialize all the bits.

Try put some nano seconds of delay on the address/en/read/write signals and see how it goes.

 

[FINALFANTASYFAN]

Uhm, whatever other signals are, BRAM data output comes to UNKNOWN right after the 1st CLK. It means at the 1st next rising edge, it turns into UNKNOWN though ADDRESS, WE, Data_in are determined and stable.

Furthermore, I implement the bit stream into board Spartan 3E, it worked!

So what is matter?

 

[kel8157]

Uhm, whatever other signals are, BRAM data output comes to UNKNOWN right after the 1st CLK. It means at the 1st next rising edge, it turns into UNKNOWN though ADDRESS, WE, Data_in are determined and stable.

Furthermore, I implement the bit stream into board Spartan 3E, it worked!

So what is matter?

if it worked in board, then it must be the timing violation.. you can double confirm with that gate level simulation, if you want to take the trouble.

In RTL simulation with BRAM models, the address/we/cs signals are delayed using clauses like the following..

#define DLY 5 ns
assign addr_out = #(`DLY) addr;

 

[FINALFANTASYFAN]

Actually, I did timing simulation.