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synchronous and Asynchronous Reset

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INS-ANI

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I am studying uses of synchronous and Asynchronous Reset and have failed to understand some point.
I will really appreciate if you can help me with it.

1) how synchronous reset synthesize to smalled flip flop?
2) logic synthesis may not identify synchronous reset and create timing issue at later stage, how?
3) asynchronous reset data path is independent of reset, hence high speed can be achieved, how? please give an example.
 

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