Synchronization in FIFO

[kaustubh]

Can anyone tell me why synchronization is required in a FIFO.
If it is to prevent some metastability, why can't we use wclk itself to do synchronization for wptr(write pointer) in read-clock domain instead of the read clock?

 

[FvM]

You should ask the question in way that's also understandable for those, how aren't just now designing a FIFO.

 

[dechen]

usually the counter in the FIFO needs to be synchronized. Use grey codeing for the counter.

 

[rjainv]

Can anyone tell me why synchronization is required in a FIFO.
If it is to prevent some metastability, why can't we use wclk itself to do synchronization for wptr(write pointer) in read-clock domain instead of the read clock?

For Synchronizing to prevent metastability, you always have to use the destination clock domain. If you are gonig to use wclk , then the wptr is clocked by wclk and is async ro rclk.

 

[kaustubh]

Can anyone tell me why synchronization is required in a FIFO.
If it is to prevent some metastability, why can't we use wclk itself to do synchronization for wptr(write pointer) in read-clock domain instead of the read clock?

For Synchronizing to prevent metastability, you always have to use the destination clock domain. If you are gonig to use wclk , then the wptr is clocked by wclk and is async ro rclk.

can you please elaborate on that ? just imagine that i am not using any synchronisers. Now i am going to give wptr(not synchronised) and rptr directly to a combo logic that compares them and generates rempty signal in the read clock domain. rempty goes high whenever rptr=wptr. This rempty is used as an input to a flop to determine if rptr has to be incremented or not. Now, rempty will continue to remain high as long as rptr=wptr. the moment wptr increments, rempty is de-asserted. i don't see why synchronization is needed in the above process.

Added after 13 minutes:


--|_|--|_|--|_|--|_|--|_|--|_|--|_|--| <-- wclk
1---2----3----4----5----6----7----8 <-- wptr

----------|_______|---------|_______ <-- rclk

In the above example, assume, wptr is being sampled by rclk using a two-stage synchronizer.clearly only values 1 and 5 are sampled at rclk... the rest of the wptr values are lost. so basically you end up overwriting if the dept of the fifo was 4. But still we use synchronizers . . . how ?

-- = high

_ = low

 

[vlsi_whiz]

There are two types of FIFO : Synchronous FIFO and Asynchronous FIFO. Synchronous FIFO's operate within the same clock frequency, ie, both read and write use a single/same clock frequency. These FIFOs can be used like data buffers.

Asynchronous FIFO's on the otherhand operate at different clocks for read and write operations. These are used as synchronization elements in a multi-clock design. In these FIFO's, since the read and write operations take place at different clocks, we need to synchronize the read and write pointers before we can compare them.

Pointer comparison is used to generate the FIFO FULL, EMPTY, HALF FULL and HALF EMPTY signals. The write pointer has to be synchronized to the read clock before it can be compared to generate the Empty signal and the read pointer has to be synchronized with the write clock for FULL signal generation.

Another problem is when we synchronize and compare the two pointers, the pointer addresses may change giving rise to incorrect FULL and EMPTY signals. To prevent this we make use of Grey style read and write pointers. This makes sure that the addresses do not change during the comparison operation.

 

[jiang]

can you please elaborate on that ? just imagine that i am not using any synchronisers. Now i am going to give wptr(not synchronised) and rptr directly to a combo logic that compares them and generates rempty signal in the read clock domain. rempty goes high whenever rptr=wptr. This rempty is used as an input to a flop to determine if rptr has to be incremented or not. Now, rempty will continue to remain high as long as rptr=wptr. the moment wptr increments, rempty is de-asserted. i don't see why synchronization is needed in the above process.


--|_|--|_|--|_|--|_|--|_|--|_|--|_|--| <-- wclk
1---2----3----4----5----6----7----8 <-- wptr

----------|_______|---------|_______ <-- rclk

In the above example, assume, wptr is being sampled by rclk using a two-stage synchronizer.clearly only values 1 and 5 are sampled at rclk... the rest of the wptr values are lost. so basically you end up overwriting if the dept of the fifo was 4. But still we use synchronizers . . . how ?

-- = high

_ = low

case 1: wclk/rclk asynchronous
The main problem is that wptr is generated by wclk domain and asychronous to rclk domain.
What happens if you use wptr signal in rclk domain directly?
1. It also has metastablility issue because of asynchronization.
2. It maybe capture wrong value because wrpt is bus and asychronous to rclk.
You cannot make sure the data skew and clock phase.

case 2: rclk is derived from wclk
It means that rclk is divided by 2,4,8,... from wclk.
You can treat wclk and rclk as synchronous.
If you don't use synchronizer, it's ok because it can be covered by P&R.
P&R tool can analyze/adjust the data and clock phase.