[SOLVED] Synchronization error in UART

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barry said:
Further, it's going to assign RX_DATA to D1 and D2 every time you receive one data
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Precisely, this is what is happening. What I want is the first data that is sent, is stored in D1. Then the next one coming is stored in D2. How do I do this?
 

For a start, you might want to use a clocked process.
 

You are not really listening to what people are telling you

1) USE A CLOCKED PROCESS
2) USE A CLOCKED PROCESS
3) USE A PROCESS WITH A CLOCK
4) You need identify when new data arrives (see post #13). You need to clear a flag when data has been read so that you can wait for it to be set on subsequent data. Back up a little bit and think about what you are actually trying to do.

a) Detect new data received, indicated by a flag
b) Read the data
c) Stick the data somewhewre
d) Clear the flag
e) repeat
 

I see that this is the original thread. electrobuz stated another thread with the code and the gated clock error. He's got a split FSM with the state register and the combinatorial logic. It does appear recommendations 1-4 were take with the added state register. ;-)
 

I am using a clocked process now. Also using register to store the value coming from the UART. Here is the code:
Code: 
C1: RX PORT MAP (CLOCK_50,UART_RXD,RX_DATA,RX_BUSY,DATA_RCVD);
R1: reg PORT MAP (Input1,CLOCK_50,L_D1,Output1);
R2: reg PORT MAP (Input2,CLOCK_50,L_D2,Output2);
FORFlag:DFF PORT MAP (Inp,resett,CLOCK_50,Outp);

process(DATA_RCVD)
begin
if DATA_RCVD = '1' then
	Inp <= '1';
else
	Inp <= '0';
end if;
end process;
 
Process(CLOCK_50,Reset)
begin
if Reset = '1' then
		NState <= 0;
elsif rising_edge(CLOCK_50) then
	case PState is
	when 0 => --idle
		if Outp = '1' then
		NState <= 1;
		end if;
	when 1 => --communication state
		D <= RX_DATA;
			if flag = 0 then
				Input1 <= D;
				L_D1 <= '1';
				flag <= 1;
			elsif flag = 1 then
				Input2 <= D;
				L_D2 <= '1';
			end if;
		resett <= '1';	
		NState <= 0;	
	end case;
	PState <= NState;
end if;	
LED <= Output1 or Output2;
end process;

The DFlipFlop is used to make the flag which is 1 when receive is complete and then made 0 once so that we can wait for the next UART communication.
The output should have been Output1 or Output2, but none of the LED's are glowing.

P.S Yes I am a persistent b*stard.
 

Oh yes. I made it 1 in case 1 when flag is 1 and data is loaded into a register. I am getting the following warning:
"WARNING:Xst:1290 - Hierarchical block <FORFlag> is unconnected in block <UART>.
It will be removed from the design.
WARNING:Xst:1710 - FF/Latch <Q_t> (without init value) has a constant value of 0 in block <DFF>. This FF/Latch will be trimmed during the optimization process."
I checked but couldnt fine any reason why Q_t is not changing and having a default value. I am sending Inp <= '1' as soon as DATA_RCVD is set. Any ideas why this is happening?
 

There are two related problems:

- Why does the design compiler remove the flag signal during optimization and can you possibly keep it, e.g. by specifying an explicit initial value?
- Does a design that never resets the signal flag make any sense? It means that the conditional code for flag = 0 will be only "executed" once after a design reset. (And the design compiler's default settings seems to follow the proverb "once doesn't count").
 

The code had some minor issues. But mainly the DATA_RCVD flag was not being set properly hence all the problem. It is working now. Thank you Barry for being so 'patient' with me.
 

barry: a broken watch will show the correct time twice a day.
 

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