synchronization cross clk domains

[gerade]

Hi, Guys,

my task is to design a module, that has 2 different clk domain, one clk may vary from 500k to 30 Mhz,for different applications. The other clk is around 30 MHz.

any one can help me pls?

thanks for your attention and time!

Best Regards

 

[eda_wiz]

Read these papers first.... further if u have any doubts .. may be I can help

**broken link removed**
http://www.sunburst-design.com/papers/CummingsSNUG2001SJ_AsyncClk_rev1_1.pdf
http://www.ece.rochester.edu/~albonesi/wced02/papers/nystrom.pdf
**broken link removed**

 

[kelvin_sg]

What you need is to design a FIFO. Theory is simple, but practice is
complicated due to the vast variations between the two clock frequency.

 

[gerade]

I am reading there papers,

FYI

there are also some papars on SNUG.

thanks and regards