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All very true.Yes, many controllers force the lower FET to conduct negative current. It decreases efficiency at light load but greatly simplifies control loop dynamics. Important when loop bandwidth must be high.
The overly high reverse current happens when the output of the error amplifier rails low (eg after an output overvoltage incident caused eg by a full-load-to-no-load-transient whatever) and the output of fet drive pulses to the high side fet stops and goes low…..since the low side sync fet is driven by the “NOT” of the high side FET signal, this then means that the sync FET is held permanently ON…..resulting in overly high reverse current in the sync FET, ..unless there is reverse current sensing in the sync FET.Where does this overly high reverse current come from ?
How can it be any higher than the peak current through the main upper switching device ?
Yes. Many buck converters are just switching the low side transistor unconditionally, in other words implement forced CCM operation. This involves higher losses at low output current but also constant loop gain, straightforward controller design and better transient response.Have you ever seen a sync buck controller that does not have the facility to detect overly high reverse current flow in the synchronous FET?
Brad, it is not a problem.
The choke current will just ramp up in the opposite direction and discharge back into the source without energy loss.
Okay you're talking about protecting the devices from huge currents, not enforcing DCM to improve efficiency. In certain applications (battery charging, as mentioned before) where the load can store large amounts of energy, this is a valid concern and you may need the controller to limit negative current. I know I've blown some FETs (on both the high and low side) in the past because I was slewing the output voltage so fast that I was getting peak currents 5-10 times the normal steady state amount.The overly high reverse current happens when the output of the error amplifier rails low (eg after an output overvoltage incident caused eg by a full-load-to-no-load-transient whatever) and the output of fet drive pulses to the high side fet stops and goes low…..since the low side sync fet is driven by the “NOT” of the high side FET signal, this then means that the sync FET is held permanently ON…..resulting in overly high reverse current in the sync FET, ..unless there is reverse current sensing in the sync FET.
Page 14 of the LM25115 datasheet explains the problem of overly high reverse current in the synchronous Buck.
https://www.ti.com/lit/ds/symlink/lm25115.pdf
I don't think it's strange, it's sufficient for many or even most synchronous buck applications which don't involve a risk of "overly high reverse current".It is actually very strange that the TPS40055 does not appear to sense for reverse current
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