why the falling edge clock on the 2nd register?
Doing that just turns the path setup requirement to 1/2 the clk clock period, instead of the full clk period.
Good tip!In this case metastability could come from the deassertion of the reset line during the reset recovery period, but note that the second register will not be affected because the input and output will have the same state when the reset line is deasserted.
Sampling the reset line by a negedge flop, just gives the maximum margin in terms of the removal/recovery restrictions.
BTW, during assertion of the asynchronous reset, the second flop could also enter to a metastable state... Is this dangerous? Probably better to add an AND gate, which would gate the asynchronous reset itself with the output of the second flop?
BTW, how would you explain that a metastable state is not dangerous if the device (flop/latch) should not change its output value?
Do you define the metastability as an oscillation of the sequential device output? Could not it be just a slow ramp/slop of the signal in its output (as a result of the racing condition between clock and reset or the data sampling on the active edge of the clock)?