Syn/STA for both rising/falling edge design

[quake]

Hello. I have a design need 1.5 frequency division, so I used both rising and falling edge of the clock. Then in sythesis and STA process, what do I need to do for constraint, seperately? Any special command should be used? And how can I gurrentee it can work correctly? Thanks

 

[quake]

anybody help?

 

[jarodz]

Did you mean the constraints of clkgen module?

Sincerely,
Jarod

 

[quake]

Yeah, almost. For DC, the clock is created, since both of the rising and falling edges are used, do I need some constraint on this clock? For PT, when timing is analysed, does it need some special cases to verify it? thanks.

 

[jarodz]

I think it only need the clock contraints. No more concern you have to take.

Sincerely,
Jarod

 

[quake]

really? thanks. If any concern has to be taken, please let me know.

 

[FvM]

As an basic issue, programmable logic has no flip-flops that are clocked on both edges. Thus the design could only be synthesized with combinational logic merging outputs from posedge and negedge flip-flops. I don't know, how the result actually looks like, but the output may have glitches if the design isn't well thought-out. This can't be prevented by clock contraints, I think.

 

[srikalyani]

Hey ,
I am attaching a ppt ..It mite help...
It has info good info on primetime and STA...
a nice informative one.