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syn problem about bus

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HolySaint

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i have a 8 bits bus a
when i syn the rtl,i found the bus a is define like this
wire [7:0] a;
but where the pin connect to a[0] and a[7] connected other wire,
and there is no use of this two bits.

what happened?
regards!
 

rakko

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check in your rtl to make sure a[0], a[7] are not accidentally shorted or left open. It seems like the synthesis tool removes these pins because it sees them as constant and ties them hi/low at the destination.
 

    HolySaint

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HolySaint

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the missed net connected nothing,
i will chenk my rtl again
thank U

but when i sim the rtl,the two nets connect normal.
the rslt is right

Added after 12 minutes:

i use this
parameter num=7;
always...
....
b<=a[num]?a:-a;
....

does this take the error?
i will try syn again.
 

lostinxlation

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HolySaint said:
parameter num=7;
always...
....
b<=a[num]?a:-a;
....

does this take the error?
i will try syn again.
if -a is negative a(not ~a)

when a[7] = 1, b[7] gets 1
when a[7] = 0, b[7] gets 1

Regardless of a[7], b[7] gets 1 so that synthesis optimized it away.

a[0] is also similar. a[7] has nothing to do with b[0]'s value, because b[0] solely depends on only a[0]'s value(take 2's comp and see what happens to a[0].). a[0] should be connected to b[0] directly. If not, I think there are more to this case, for example, b[0] isn't used or a[0] got constant value on upstream logic.
 

    HolySaint

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HolySaint

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lostinxlation said:
HolySaint said:
parameter num=7;
always...
....
b<=a[num]?a:-a;
....

does this take the error?
i will try syn again.
if -a is negative a(not ~a)

when a[7] = 1, b[7] gets 1
when a[7] = 0, b[7] gets 1

Regardless of a[7], b[7] gets 1 so that synthesis optimized it away.

a[0] is also similar. a[7] has nothing to do with b[0]'s value, because b[0] solely depends on only a[0]'s value(take 2's comp and see what happens to a[0].). a[0] should be connected to b[0] directly. If not, I think there are more to this case, for example, b[0] isn't used or a[0] got constant value on upstream logic.

thank you, i found that the a[7] is also used in other submodule
and b[7] is always behigh,but other submodule use a[7],so i think the syn tool
should not remove the wire.

Added after 6 minutes:

and a is an output port in this module,it input to other module
 

lostinxlation

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[quote="HolySaint
and a is an output port in this module,it input to other module[/quote]
HOw a is generated ? And what synthesis log says ?
 

HolySaint

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the log said nothing
always @(posedge clk or ...)
...
a <= 。。。
i will check the value agian

the mismatch is found by ncsim

Added after 14 minutes:

i use flatten compile

Added after 15 minutes:

lostinxlation said:
[quote="HolySaint
and a is an output port in this module,it input to other module
HOw a is generated ? And what synthesis log says ?[/quote]

reg [15:0] re;
wire [7:0] df = re[15]? 8'h81:8'h7f;
timing_delt<=((re[15]&~(&re[14:7]))|(~re[15]&(|re[14:7])))?df:re[7:0];
 

lostinxlation

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HolySaint said:
reg [15:0] re;
wire [7:0] df = re[15]? 8'h81:8'h7f;
timing_delt<=((re[15]&~(&re[14:7]))|(~re[15]&(|re[14:7])))?df:re[7:0];
doesn't the synthesis take r[15] instead of timing_delt[7] to drive the target module ? Logically, r[15] and timing_delt[7] are the same except one is floped,another isn't, and if re[*] is flopped somewhere, it might use that output in place of timing_delt[7].

Code:
r[15]  r[7]      timing_delt
--------------------------------
  0      0       re[7:0]/0111_1111
  0      1       0111_1111
  1      0       1000_0001
  1      1       re[7:0]/1000_0001

timing_delt[7,0](a[7:0]) doesn't seem constant (if re[*] bit pattern is totally arbitrary) and shouldn't be removed, but re[*] is actually random ?

formal verification can tell.
 

HolySaint

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a si timing_delt, i forgot to say
a is an output reg
re is just a reg

reg [15] re;
wire [7] df = re[15]? 8'h81:8'h7f;
always .
a<=((re[15]&~(&re[14]))|(~re[15]&(|re[14])))?df:re[7];
...............
and there is submodule use like this
fa fa1(...,...,a);

so , i think there is no replace wire.
by the way,i will try to make a small example for this.
thank u again.

Added after 12 minutes:

lostinxlation said:
HolySaint said:
reg [15:0] re;
wire [7:0] df = re[15]? 8'h81:8'h7f;
timing_delt<=((re[15]&~(&re[14:7]))|(~re[15]&(|re[14:7])))?df:re[7:0];
doesn't the synthesis take r[15] instead of timing_delt[7] to drive the target module ? Logically, r[15] and timing_delt[7] are the same except one is floped,another isn't, and if re[*] is flopped somewhere, it might use that output in place of timing_delt[7].

Code:
r[15]  r[7]      timing_delt
--------------------------------
  0      0       re[7:0]/0111_1111
  0      1       0111_1111
  1      0       1000_0001
  1      1       re[7:0]/1000_0001

timing_delt[7,0](a[7:0]) doesn't seem constant (if re[*] bit pattern is totally arbitrary) and shouldn't be removed, but re[*] is actually random ?

formal verification can tell.

Code:
module u1(a,...);
...
output [7:0] a;
...
reg    [7:0] a;

reg [15:0] re; 
wire [7:0] df = re[15]? 8'h81:8'h7f; 

always ... 
a<=((re[15]&~(&re[14:7]))|(~re[15]&(|re[14:7])))?df:re[7:0]; 
............... 


fa fa1(...,...,a);
fa fa2(...,...,a);

endmodule

module u2(a,...);
input  [7:0] a;
.....
endmodule

module u(...)
...
wire  [7:0] a;

u1 u1(a,...);
u2 u2(a,...);
...
endmodule


the top is u,but in the netlist,

wire [7:0] a;
but the a[7] and a [0] is Z.

------------------------------------
may be the logic make mistake,but there is only
one output rslt.
Regards!
 

lostinxlation

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so, a[0] and [7] output pins of u1 aren't driven, and input a[0] and a[7] of u2 is set to zero. Now the question is are there flops for a[0] and a[7] in u1 netlist ?
 

HolySaint

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lostinxlation said:
so, a[0] and [7] output pins of u1 aren't driven, and input a[0] and a[7] of u2 is set to zero. Now the question is are there flops for a[0] and a[7] in u1 netlist ?
Code:
module u(d1,clk,rst,d2);

input  clk,rst;
input  [7:0] d1;
output [15:0] d2;

wire   [7:0] mark_a;

u1 u1(mark_a,clk,rst,d1);
u2 u2(mark_a,clk,rst,d2);

endmodule


// sub module


module u1(a,clk,rst,d1);

input  clk,rst;
input  [7:0] d1;
output [7:0] a;

reg    [7:0] a;

reg    [15:0] re;
wire   [ 7:0] df;
assign df = re[15]? 8'h81:8'h7f;

always @(posedge clk or negedge rst)
  if(!rst) re <= 0;
  else     re <= d1 << 2 + d1;

always @(posedge clk or negedge rst)
  if(!rst) a <= 0;
  else     a <= ((re[15]&~(&re[14:7]))|(~re[15]&(|re[14:7])))?df:re[7:0];

endmodule

module u2(a,clk,rst,d2);

input  clk,rst;
input  [7:0] a;
output [15:0] d2;

assign d2 = a << 2 + a;

endmodule

netlist will be shown after 3 mins [/code]

Added after 7 minutes:

Code:
module u ( d1, clk, rst, d2 );
  input [7:0] d1;
  output [15:0] d2;
  input clk, rst;
  wire   \u1/N36 , \u1/N35 , \u1/N34 , \u1/N33 , \u1/N32 , \u1/N31 , \u1/N30 ,
         \u1/N29 , \u1/N26 , \u1/N25 , \u1/N24 , \u1/N23 , \u1/N22 , \u1/N21 ,
         \u1/N20 , \u1/N19 , \u1/N18 , \u1/N17 , \u1/N16 , \u1/N15 , \u1/N14 ,
         \u1/N13 , \u1/N12 , \u1/N11 , \u1/N10 , \u1/N9 , \u1/N8 , \u1/N7 ,
         \u1/N6 , \u1/N5 , \u1/N4 , \u1/N3 , \u1/N2 , \u1/re[0] , \u1/re[1] ,
         \u1/re[2] , \u1/re[3] , \u1/re[4] , \u1/re[5] , \u1/re[6] ,
         \u1/re[7] , \u1/re[8] , \u1/re[9] , \u1/re[10] , \u1/re[11] ,
         \u1/re[12] , \u1/re[13] , \u1/re[14] , \u2/N8 , \u2/N7 , \u2/N6 ,
         \u2/N5 , \u2/N4 , \u2/N3 , \u2/N2 , \u2/N0 , n10, n11, n12, n13, n14,
         n15, n16, n17, n18, n19, \u2/sll_46/ML_int[4][8] ,
         \u2/sll_46/ML_int[4][9] , \u2/sll_46/ML_int[4][10] ,
         \u2/sll_46/ML_int[4][11] , \u2/sll_46/ML_int[4][12] ,
         \u2/sll_46/ML_int[4][13] , \u2/sll_46/ML_int[4][14] ,
         \u2/sll_46/ML_int[3][4] , \u2/sll_46/ML_int[3][5] ,
         \u2/sll_46/ML_int[3][6] , \u2/sll_46/ML_int[3][7] ,
         \u2/sll_46/ML_int[3][12] , \u2/sll_46/ML_int[3][13] ,
         \u2/sll_46/ML_int[3][14] , \u2/sll_46/ML_int[2][0] ,
         \u2/sll_46/ML_int[2][1] , \u2/sll_46/ML_int[2][2] ,
         \u2/sll_46/ML_int[2][3] , \u2/sll_46/ML_int[2][4] ,
         \u2/sll_46/ML_int[2][5] , \u2/sll_46/ML_int[2][6] ,
         \u2/sll_46/ML_int[2][7] , \u2/sll_46/ML_int[2][8] ,
         \u2/sll_46/ML_int[2][9] , \u2/sll_46/ML_int[2][10] ,
         \u2/sll_46/ML_int[1][0] , \u2/sll_46/ML_int[1][1] ,
         \u2/sll_46/ML_int[1][2] , \u2/sll_46/ML_int[1][3] ,
         \u2/sll_46/ML_int[1][4] , \u2/sll_46/ML_int[1][5] ,
         \u2/sll_46/ML_int[1][6] , \u2/sll_46/ML_int[1][7] ,
         \u2/sll_46/MR_int[1][7] , \u2/sll_46/SHMAG[0] , \u2/sll_46/SHMAG[1] ,
         \u2/sll_46/SHMAG[2] , \u2/sll_46/SHMAG[3] ,
         \u2/sll_46/temp_int_SH[0] , \u2/sll_46/temp_int_SH[1] ,
         \u2/sll_46/temp_int_SH[2] , \u2/sll_46/temp_int_SH[3] ,
         \u2/add_46/carry[2] , \u2/add_46/carry[3] , \u2/add_46/carry[4] ,
         \u2/add_46/carry[5] , \u2/add_46/carry[6] , \u2/add_46/carry[7] ,
         \u1/sll_32/ML_int[4][8] , \u1/sll_32/ML_int[4][9] ,
         \u1/sll_32/ML_int[4][10] , \u1/sll_32/ML_int[4][11] ,
         \u1/sll_32/ML_int[4][13] , \u1/sll_32/ML_int[4][14] ,
         \u1/sll_32/ML_int[3][4] , \u1/sll_32/ML_int[3][5] ,
         \u1/sll_32/ML_int[3][6] , \u1/sll_32/ML_int[3][7] ,
         \u1/sll_32/ML_int[3][12] , \u1/sll_32/ML_int[3][13] ,
         \u1/sll_32/ML_int[3][14] , \u1/sll_32/ML_int[2][0] ,
         \u1/sll_32/ML_int[2][1] , \u1/sll_32/ML_int[2][2] ,
         \u1/sll_32/ML_int[2][3] , \u1/sll_32/ML_int[2][4] ,
         \u1/sll_32/ML_int[2][5] , \u1/sll_32/ML_int[2][6] ,
         \u1/sll_32/ML_int[2][7] , \u1/sll_32/ML_int[2][8] ,
         \u1/sll_32/ML_int[2][9] , \u1/sll_32/ML_int[2][10] ,
         \u1/sll_32/ML_int[1][0] , \u1/sll_32/ML_int[1][1] ,
         \u1/sll_32/ML_int[1][2] , \u1/sll_32/ML_int[1][3] ,
         \u1/sll_32/ML_int[1][4] , \u1/sll_32/ML_int[1][5] ,
         \u1/sll_32/ML_int[1][6] , \u1/sll_32/ML_int[1][7] ,
         \u1/sll_32/MR_int[1][7] , \u1/sll_32/SHMAG[0] , \u1/sll_32/SHMAG[1] ,
         \u1/sll_32/SHMAG[2] , \u1/sll_32/SHMAG[3] , \u1/sll_32/SHMAG[4] ,
         \u1/sll_32/temp_int_SH[0] , \u1/sll_32/temp_int_SH[1] ,
         \u1/sll_32/temp_int_SH[2] , \u1/sll_32/temp_int_SH[3] ,
         \u1/add_32/carry[2] , \u1/add_32/carry[3] , \u1/add_32/carry[4] ,
         \u1/add_32/carry[5] , \u1/add_32/carry[6] , \u1/add_32/carry[7] , n20,
         n21, n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34,
         n35, n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48,
         n49, n50, n51, n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62,
         n63, n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, n74, n75, n76,
         n77, n78, n79, n80, n81, n82, n83, n84, n85, n86, n87, n88, n89, n90,
         n91, n92, n93, n94, n95, n96;
  wire   [7:0] mark_a;
  assign \u1/N2  = d1[0];
  assign \u1/add_32/carry[2]  = d1[1];

  DFFRHQX1 \u1/a_reg[0]  ( .D(\u1/N29 ), .CK(clk), .RN(rst), .Q(\u2/N0 ) );
  DFFRHQX1 \u1/a_reg[7]  ( .D(\u1/N36 ), .CK(clk), .RN(rst), .Q(mark_a[7]) );
  DFFRHQX1 \u1/a_reg[6]  ( .D(\u1/N35 ), .CK(clk), .RN(rst), .Q(mark_a[6]) );
  DFFRHQX1 \u1/a_reg[5]  ( .D(\u1/N34 ), .CK(clk), .RN(rst), .Q(mark_a[5]) );
  DFFRHQX1 \u1/a_reg[4]  ( .D(\u1/N33 ), .CK(clk), .RN(rst), .Q(mark_a[4]) );
  DFFRHQX1 \u1/a_reg[3]  ( .D(\u1/N32 ), .CK(clk), .RN(rst), .Q(mark_a[3]) );
  DFFRHQX1 \u1/a_reg[2]  ( .D(\u1/N31 ), .CK(clk), .RN(rst), .Q(mark_a[2]) );
  DFFRHQX1 \u1/a_reg[1]  ( .D(\u1/N30 ), .CK(clk), .RN(rst), .Q(
        \u2/add_46/carry[2] ) );
  DFFRHQX1 \u1/re_reg[1]  ( .D(n20), .CK(clk), .RN(rst), .Q(\u1/re[1] ) );
  DFFRHQX1 \u1/re_reg[2]  ( .D(\u1/N13 ), .CK(clk), .RN(rst), .Q(\u1/re[2] )
         );
  DFFRHQX1 \u1/re_reg[3]  ( .D(n22), .CK(clk), .RN(rst), .Q(\u1/re[3] ) );
  DFFRHQX1 \u1/re_reg[4]  ( .D(n52), .CK(clk), .RN(rst), .Q(\u1/re[4] ) );
  DFFRHQX1 \u1/re_reg[5]  ( .D(n53), .CK(clk), .RN(rst), .Q(\u1/re[5] ) );
  DFFRHQX1 \u1/re_reg[6]  ( .D(n54), .CK(clk), .RN(rst), .Q(\u1/re[6] ) );
  DFFRHQX1 \u1/re_reg[0]  ( .D(\u1/N11 ), .CK(clk), .RN(rst), .Q(\u1/re[0] )
         );
  DFFRHQX1 \u1/re_reg[8]  ( .D(\u1/N19 ), .CK(clk), .RN(rst), .Q(\u1/re[8] )
         );
  DFFRHQX1 \u1/re_reg[7]  ( .D(n56), .CK(clk), .RN(rst), .Q(\u1/re[7] ) );
  DFFRHQX1 \u1/re_reg[11]  ( .D(n59), .CK(clk), .RN(rst), .Q(\u1/re[11] ) );
  DFFRHQX1 \u1/re_reg[10]  ( .D(n60), .CK(clk), .RN(rst), .Q(\u1/re[10] ) );
  DFFRHQX1 \u1/re_reg[14]  ( .D(n29), .CK(clk), .RN(rst), .Q(\u1/re[14] ) );
  DFFRHQX1 \u1/re_reg[12]  ( .D(\u1/N23 ), .CK(clk), .RN(rst), .Q(\u1/re[12] )
         );
  DFFRHQX1 \u1/re_reg[9]  ( .D(n63), .CK(clk), .RN(rst), .Q(\u1/re[9] ) );
  DFFRHQX1 \u1/re_reg[13]  ( .D(\u1/N24 ), .CK(clk), .RN(rst), .Q(\u1/re[13] )
         );
  MX2X1 \u2/sll_46/M1_0_7  ( .A(mark_a[7]), .B(mark_a[6]), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][7] ) );
  MX2X1 \u2/sll_46/M1_0_1  ( .A(\u2/add_46/carry[2] ), .B(\u2/N0 ), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][1] ) );
  MX2X1 \u2/sll_46/M1_0_5  ( .A(mark_a[5]), .B(mark_a[4]), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][5] ) );
  MX2X1 \u2/sll_46/M1_0_4  ( .A(mark_a[4]), .B(mark_a[3]), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][4] ) );
  MX2X1 \u2/sll_46/M1_0_6  ( .A(mark_a[6]), .B(mark_a[5]), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][6] ) );
  MX2X1 \u2/sll_46/M1_0_3  ( .A(mark_a[3]), .B(mark_a[2]), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][3] ) );
  MX2X1 \u2/sll_46/M1_0_2  ( .A(mark_a[2]), .B(\u2/add_46/carry[2] ), .S0(
        \u2/sll_46/temp_int_SH[0] ), .Y(\u2/sll_46/ML_int[1][2] ) );
  MX2X1 \u2/sll_46/M1_1_7  ( .A(\u2/sll_46/ML_int[1][7] ), .B(
        \u2/sll_46/ML_int[1][5] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][7] ) );
  MX2X1 \u2/sll_46/M1_1_8  ( .A(\u2/sll_46/MR_int[1][7] ), .B(
        \u2/sll_46/ML_int[1][6] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][8] ) );
  MX2X1 \u2/sll_46/M1_1_6  ( .A(\u2/sll_46/ML_int[1][6] ), .B(
        \u2/sll_46/ML_int[1][4] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][6] ) );
  MX2X1 \u2/sll_46/M1_1_5  ( .A(\u2/sll_46/ML_int[1][5] ), .B(
        \u2/sll_46/ML_int[1][3] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][5] ) );
  MX2X1 \u2/sll_46/M1_1_4  ( .A(\u2/sll_46/ML_int[1][4] ), .B(
        \u2/sll_46/ML_int[1][2] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][4] ) );
  MX2X1 \u2/sll_46/M1_1_3  ( .A(\u2/sll_46/ML_int[1][3] ), .B(
        \u2/sll_46/ML_int[1][1] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][3] ) );
  MX2X1 \u2/sll_46/M1_1_2  ( .A(\u2/sll_46/ML_int[1][2] ), .B(
        \u2/sll_46/ML_int[1][0] ), .S0(\u2/sll_46/temp_int_SH[1] ), .Y(
        \u2/sll_46/ML_int[2][2] ) );
  MX2X1 \u2/sll_46/M1_3_14  ( .A(\u2/sll_46/ML_int[3][14] ), .B(
        \u2/sll_46/ML_int[3][6] ), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][14] ) );
  MX2X1 \u2/sll_46/M1_3_13  ( .A(\u2/sll_46/ML_int[3][13] ), .B(
        \u2/sll_46/ML_int[3][5] ), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][13] ) );
  MX2X1 \u2/sll_46/M1_3_12  ( .A(\u2/sll_46/ML_int[3][12] ), .B(
        \u2/sll_46/ML_int[3][4] ), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][12] ) );
  MX2X1 \u2/sll_46/M1_2_7  ( .A(\u2/sll_46/ML_int[2][7] ), .B(
        \u2/sll_46/ML_int[2][3] ), .S0(\u2/sll_46/temp_int_SH[2] ), .Y(
        \u2/sll_46/ML_int[3][7] ) );
  MX2X1 \u2/sll_46/M1_2_6  ( .A(\u2/sll_46/ML_int[2][6] ), .B(
        \u2/sll_46/ML_int[2][2] ), .S0(\u2/sll_46/temp_int_SH[2] ), .Y(
        \u2/sll_46/ML_int[3][6] ) );
  MX2X1 \u2/sll_46/M1_2_5  ( .A(\u2/sll_46/ML_int[2][5] ), .B(
        \u2/sll_46/ML_int[2][1] ), .S0(\u2/sll_46/temp_int_SH[2] ), .Y(
        \u2/sll_46/ML_int[3][5] ) );
  MX2X1 \u2/sll_46/M1_2_4  ( .A(\u2/sll_46/ML_int[2][4] ), .B(
        \u2/sll_46/ML_int[2][0] ), .S0(\u2/sll_46/temp_int_SH[2] ), .Y(
        \u2/sll_46/ML_int[3][4] ) );
  MX2X1 \u1/sll_32/M1_2_7  ( .A(\u1/sll_32/ML_int[2][7] ), .B(
        \u1/sll_32/ML_int[2][3] ), .S0(\u1/sll_32/temp_int_SH[2] ), .Y(
        \u1/sll_32/ML_int[3][7] ) );
  MX2X1 \u1/sll_32/M1_2_6  ( .A(\u1/sll_32/ML_int[2][6] ), .B(
        \u1/sll_32/ML_int[2][2] ), .S0(\u1/sll_32/temp_int_SH[2] ), .Y(
        \u1/sll_32/ML_int[3][6] ) );
  MX2XL \u1/sll_32/M1_0_7  ( .A(n64), .B(d1[6]), .S0(
        \u1/sll_32/temp_int_SH[0] ), .Y(\u1/sll_32/ML_int[1][7] ) );
  MX2XL \u1/sll_32/M1_0_5  ( .A(d1[5]), .B(d1[4]), .S0(
        \u1/sll_32/temp_int_SH[0] ), .Y(\u1/sll_32/ML_int[1][5] ) );
  MX2XL \u1/sll_32/M1_0_1  ( .A(\u1/add_32/carry[2] ), .B(\u1/N2 ), .S0(
        \u1/sll_32/temp_int_SH[0] ), .Y(\u1/sll_32/ML_int[1][1] ) );
  MX2XL \u1/sll_32/M1_0_3  ( .A(n27), .B(d1[2]), .S0(
        \u1/sll_32/temp_int_SH[0] ), .Y(\u1/sll_32/ML_int[1][3] ) );
  MX2XL \u1/sll_32/M1_0_6  ( .A(d1[6]), .B(d1[5]), .S0(
        \u1/sll_32/temp_int_SH[0] ), .Y(\u1/sll_32/ML_int[1][6] ) );
  MX2XL \u1/sll_32/M1_0_4  ( .A(d1[4]), .B(n27), .S0(
        \u1/sll_32/temp_int_SH[0] ), .Y(\u1/sll_32/ML_int[1][4] ) );
  MX2XL \u1/sll_32/M1_1_8  ( .A(\u1/sll_32/MR_int[1][7] ), .B(
        \u1/sll_32/ML_int[1][6] ), .S0(\u1/sll_32/temp_int_SH[1] ), .Y(
        \u1/sll_32/ML_int[2][8] ) );
  MX2XL \u1/sll_32/M1_1_7  ( .A(\u1/sll_32/ML_int[1][7] ), .B(
        \u1/sll_32/ML_int[1][5] ), .S0(\u1/sll_32/temp_int_SH[1] ), .Y(
        \u1/sll_32/ML_int[2][7] ) );
  MX2XL \u1/sll_32/M1_1_6  ( .A(\u1/sll_32/ML_int[1][6] ), .B(
        \u1/sll_32/ML_int[1][4] ), .S0(\u1/sll_32/temp_int_SH[1] ), .Y(
        \u1/sll_32/ML_int[2][6] ) );
  MX2XL \u1/sll_32/M1_2_4  ( .A(\u1/sll_32/ML_int[2][4] ), .B(
        \u1/sll_32/ML_int[2][0] ), .S0(\u1/sll_32/temp_int_SH[2] ), .Y(
        \u1/sll_32/ML_int[3][4] ) );
  DFFRHQXL \u1/re_reg[15]  ( .D(\u1/N26 ), .CK(clk), .RN(rst), .Q(\u1/N36 ) );
  MX2XL \u1/sll_32/M1_1_5  ( .A(\u1/sll_32/ML_int[1][5] ), .B(
        \u1/sll_32/ML_int[1][3] ), .S0(\u1/sll_32/temp_int_SH[1] ), .Y(
        \u1/sll_32/ML_int[2][5] ) );
  MX2XL \u1/sll_32/M1_3_13  ( .A(\u1/sll_32/ML_int[3][13] ), .B(
        \u1/sll_32/ML_int[3][5] ), .S0(\u1/sll_32/temp_int_SH[3] ), .Y(
        \u1/sll_32/ML_int[4][13] ) );
  DLY4X1 U22 ( .A(\u1/N12 ), .Y(n20) );
  OR2XL U23 ( .A(n84), .B(n81), .Y(n51) );
  DLY2X1 U24 ( .A(\u1/sll_32/SHMAG[3] ), .Y(n74) );
  AOI21XL U25 ( .A0(\u1/N5 ), .A1(n79), .B0(n78), .Y(\u1/sll_32/SHMAG[3] ) );
  INVXL U26 ( .A(n37), .Y(\u1/sll_32/ML_int[2][2] ) );
  DLY4X1 U27 ( .A(n82), .Y(n21) );
  OR2XL U28 ( .A(n84), .B(n21), .Y(n50) );
  CLKBUFX1 U29 ( .A(\u1/N14 ), .Y(n22) );
  OR2XL U30 ( .A(n84), .B(n83), .Y(n49) );
  CLKBUFXL U31 ( .A(\u1/sll_32/ML_int[3][4] ), .Y(n23) );
  DLY4X1 U32 ( .A(\u1/N15 ), .Y(n52) );
  DLY2X1 U33 ( .A(\u1/sll_32/ML_int[3][5] ), .Y(n24) );
  NAND2XL U34 ( .A(\u1/sll_32/ML_int[1][1] ), .B(\u1/sll_32/SHMAG[1] ), .Y(n38) );
  DLY2X1 U35 ( .A(n55), .Y(n54) );
  NOR2BX4 U36 ( .AN(\u1/sll_32/ML_int[3][6] ), .B(n84), .Y(\u1/N17 ) );
  MXI2XL U37 ( .A(\u1/sll_32/ML_int[1][2] ), .B(\u1/sll_32/ML_int[1][0] ), 
        .S0(\u1/sll_32/temp_int_SH[1] ), .Y(n37) );
  DLY2X1 U38 ( .A(n48), .Y(n25) );
  OR2X4 U39 ( .A(n84), .B(n80), .Y(n48) );
  DLY4X1 U40 ( .A(n35), .Y(n26) );
  NAND2X4 U41 ( .A(\u1/sll_32/ML_int[1][0] ), .B(\u1/sll_32/SHMAG[1] ), .Y(n35) );
  INVX12 U42 ( .A(n28), .Y(\u1/N19 ) );
  CLKBUFX1 U43 ( .A(d1[3]), .Y(n27) );
  DLY4X1 U44 ( .A(n47), .Y(n28) );
  NAND2XL U45 ( .A(\u1/sll_32/ML_int[4][8] ), .B(n85), .Y(n47) );
  MX2X1 U46 ( .A(\u1/sll_32/ML_int[1][2] ), .B(\u1/sll_32/ML_int[1][4] ), .S0(
        \u1/sll_32/SHMAG[1] ), .Y(\u1/sll_32/ML_int[2][4] ) );
  DLY2X1 U47 ( .A(\u1/N22 ), .Y(n58) );
  CLKBUFXL U48 ( .A(n61), .Y(n60) );
  AND2X2 U49 ( .A(\u1/sll_32/ML_int[4][10] ), .B(n85), .Y(\u1/N21 ) );
  DLY4X1 U50 ( .A(\u1/N25 ), .Y(n29) );
  AND2X2 U51 ( .A(\u1/sll_32/ML_int[4][14] ), .B(n85), .Y(\u1/N25 ) );
  MXI2XL U52 ( .A(\u1/sll_32/ML_int[3][14] ), .B(\u1/sll_32/ML_int[3][6] ), 
        .S0(\u1/sll_32/temp_int_SH[3] ), .Y(n46) );
  INVXL U53 ( .A(n30), .Y(\u1/N23 ) );
  DLY4X1 U54 ( .A(n44), .Y(n30) );
  NAND2BX2 U55 ( .AN(n45), .B(n85), .Y(n44) );
  MXI2XL U56 ( .A(\u1/sll_32/ML_int[3][12] ), .B(\u1/sll_32/ML_int[3][4] ), 
        .S0(\u1/sll_32/temp_int_SH[3] ), .Y(n45) );
  AND2XL U57 ( .A(\u1/sll_32/ML_int[2][8] ), .B(\u1/sll_32/temp_int_SH[2] ), 
        .Y(\u1/sll_32/ML_int[3][12] ) );
  MX2XL U58 ( .A(\u1/add_32/carry[2] ), .B(d1[2]), .S0(\u1/sll_32/SHMAG[0] ), 
        .Y(\u1/sll_32/ML_int[1][2] ) );
  DLY2X1 U59 ( .A(\u1/sll_32/ML_int[4][9] ), .Y(n31) );
  MXI2X4 U60 ( .A(n67), .B(n81), .S0(\u1/sll_32/temp_int_SH[3] ), .Y(
        \u1/sll_32/ML_int[4][9] ) );
  DLY4X1 U61 ( .A(\u1/N20 ), .Y(n63) );
  AND2X4 U62 ( .A(n31), .B(n85), .Y(\u1/N20 ) );
  MXI2XL U63 ( .A(\u1/sll_32/ML_int[2][9] ), .B(\u1/sll_32/ML_int[2][5] ), 
        .S0(\u1/sll_32/temp_int_SH[2] ), .Y(n67) );
  INVXL U64 ( .A(n32), .Y(\u1/N24 ) );
  DLY4X1 U65 ( .A(n43), .Y(n32) );
  AND2XL U66 ( .A(\u1/sll_32/temp_int_SH[2] ), .B(\u1/sll_32/ML_int[2][9] ), 
        .Y(\u1/sll_32/ML_int[3][13] ) );
  DLY4X1 U67 ( .A(n36), .Y(n33) );
  MXI2X4 U68 ( .A(\u1/sll_32/ML_int[1][3] ), .B(\u1/sll_32/ML_int[1][1] ), 
        .S0(\u1/sll_32/temp_int_SH[1] ), .Y(n36) );
  DLY4X1 U69 ( .A(n41), .Y(n34) );
  NAND2BX4 U70 ( .AN(n42), .B(n85), .Y(n41) );
  NAND2XL U71 ( .A(\u1/sll_32/temp_int_SH[3] ), .B(\u1/sll_32/ML_int[3][7] ), 
        .Y(n42) );
  NAND2X4 U72 ( .A(n85), .B(\u1/sll_32/ML_int[4][13] ), .Y(n43) );
  AOI21XL U73 ( .A0(n79), .A1(\u1/N2 ), .B0(n78), .Y(\u1/sll_32/SHMAG[0] ) );
  INVXL U74 ( .A(n75), .Y(n79) );
  INVXL U75 ( .A(n77), .Y(n78) );
  AOI211X1 U76 ( .A0(n90), .A1(\u2/N4 ), .B0(n89), .C0(\u2/N8 ), .Y(n96) );
  AND2X2 U77 ( .A(\u1/sll_32/ML_int[4][11] ), .B(n85), .Y(\u1/N22 ) );
  INVXL U78 ( .A(n39), .Y(n85) );
  AOI2BB1X1 U79 ( .A0N(\u2/add_46/carry[2] ), .A1N(n86), .B0(n89), .Y(
        \u2/sll_46/SHMAG[1] ) );
  MX2X4 U80 ( .A(\u1/sll_32/ML_int[2][1] ), .B(\u1/sll_32/ML_int[2][5] ), .S0(
        n73), .Y(\u1/sll_32/ML_int[3][5] ) );
  AND3X2 U81 ( .A(\u2/sll_46/ML_int[3][7] ), .B(n96), .C(
        \u2/sll_46/temp_int_SH[3] ), .Y(d2[15]) );
  INVX1 U82 ( .A(n26), .Y(\u1/sll_32/ML_int[2][0] ) );
  INVX1 U83 ( .A(n33), .Y(\u1/sll_32/ML_int[2][3] ) );
  INVX1 U84 ( .A(n38), .Y(\u1/sll_32/ML_int[2][1] ) );
  OR2X2 U85 ( .A(n40), .B(\u1/N10 ), .Y(n39) );
  INVX1 U86 ( .A(\u1/sll_32/SHMAG[4] ), .Y(n40) );
  INVX1 U87 ( .A(n34), .Y(\u1/N26 ) );
  INVX1 U88 ( .A(n46), .Y(\u1/sll_32/ML_int[4][14] ) );
  INVX1 U89 ( .A(n25), .Y(\u1/N11 ) );
  INVX1 U90 ( .A(n49), .Y(\u1/N14 ) );
  INVX1 U91 ( .A(n50), .Y(\u1/N13 ) );
  INVX1 U92 ( .A(n51), .Y(\u1/N12 ) );
  AOI21X1 U93 ( .A0(\u1/N4 ), .A1(n79), .B0(n78), .Y(\u1/sll_32/SHMAG[2] ) );
  MXI2X1 U94 ( .A(n65), .B(n83), .S0(\u1/sll_32/temp_int_SH[3] ), .Y(
        \u1/sll_32/ML_int[4][11] ) );
  NOR2BX1 U95 ( .AN(\u1/sll_32/ML_int[3][7] ), .B(n84), .Y(\u1/N18 ) );
  NAND2XL U96 ( .A(\u1/sll_32/ML_int[2][1] ), .B(n73), .Y(n81) );
  NAND2XL U97 ( .A(\u1/sll_32/ML_int[2][2] ), .B(n73), .Y(n82) );
  NAND2XL U98 ( .A(\u1/sll_32/ML_int[2][3] ), .B(n73), .Y(n83) );
  NOR2BXL U99 ( .AN(n23), .B(n84), .Y(\u1/N15 ) );
  DLY4X1 U100 ( .A(\u1/N16 ), .Y(n53) );
  NOR2BXL U101 ( .AN(n24), .B(n84), .Y(\u1/N16 ) );
  DLY4X1 U102 ( .A(\u1/N17 ), .Y(n55) );
  NAND2XL U103 ( .A(\u1/sll_32/ML_int[2][0] ), .B(n73), .Y(n80) );
  MXI2XL U104 ( .A(n62), .B(\u1/sll_32/ML_int[2][4] ), .S0(
        \u1/sll_32/temp_int_SH[2] ), .Y(n68) );
  XOR2XL U105 ( .A(n27), .B(\u1/add_32/carry[3] ), .Y(\u1/N5 ) );
  MXI2XL U106 ( .A(n68), .B(n80), .S0(\u1/sll_32/temp_int_SH[3] ), .Y(
        \u1/sll_32/ML_int[4][8] ) );
  CLKBUFX1 U107 ( .A(n57), .Y(n56) );
  DLY4X1 U108 ( .A(\u1/N18 ), .Y(n57) );
  NAND2XL U109 ( .A(n85), .B(n74), .Y(n84) );
  NAND2X4 U110 ( .A(\u1/sll_32/temp_int_SH[2] ), .B(\u1/sll_32/ML_int[2][7] ), 
        .Y(n65) );
  DLY4X1 U111 ( .A(n58), .Y(n59) );
  DLY4X1 U112 ( .A(\u1/N21 ), .Y(n61) );
  CLKBUFX1 U113 ( .A(\u1/sll_32/ML_int[2][8] ), .Y(n62) );
  AND2XL U114 ( .A(\u1/N2 ), .B(\u1/sll_32/SHMAG[0] ), .Y(
        \u1/sll_32/ML_int[1][0] ) );
  DLY4X1 U115 ( .A(\u1/sll_32/SHMAG[2] ), .Y(n73) );
  XOR2XL U116 ( .A(d1[2]), .B(\u1/add_32/carry[2] ), .Y(\u1/N4 ) );
  CLKBUFX1 U117 ( .A(d1[7]), .Y(n64) );
  AND2XL U118 ( .A(\u1/sll_32/temp_int_SH[1] ), .B(\u1/sll_32/ML_int[1][7] ), 
        .Y(\u1/sll_32/ML_int[2][9] ) );
  AND2XL U119 ( .A(n64), .B(\u1/add_32/carry[7] ), .Y(\u1/N10 ) );
  MXI2X1 U120 ( .A(n66), .B(n82), .S0(\u1/sll_32/temp_int_SH[3] ), .Y(
        \u1/sll_32/ML_int[4][10] ) );
  MXI2X1 U121 ( .A(\u1/sll_32/ML_int[2][10] ), .B(\u1/sll_32/ML_int[2][6] ), 
        .S0(\u1/sll_32/temp_int_SH[2] ), .Y(n66) );
  NOR2X1 U122 ( .A(n95), .B(n91), .Y(d2[0]) );
  NOR2X1 U123 ( .A(n95), .B(n92), .Y(d2[1]) );
  NOR2X1 U124 ( .A(n95), .B(n93), .Y(d2[2]) );
  NOR2X1 U125 ( .A(n95), .B(n94), .Y(d2[3]) );
  NOR2BX1 U126 ( .AN(\u2/sll_46/ML_int[3][4] ), .B(n95), .Y(d2[4]) );
  NOR2BX1 U127 ( .AN(\u2/sll_46/ML_int[3][5] ), .B(n95), .Y(d2[5]) );
  NOR2BX1 U128 ( .AN(\u2/sll_46/ML_int[3][6] ), .B(n95), .Y(d2[6]) );
  NOR2BX1 U129 ( .AN(\u2/sll_46/ML_int[3][7] ), .B(n95), .Y(d2[7]) );
  MXI2X1 U130 ( .A(n69), .B(n91), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][8] ) );
  MXI2X1 U131 ( .A(\u2/sll_46/ML_int[2][8] ), .B(\u2/sll_46/ML_int[2][4] ), 
        .S0(\u2/sll_46/temp_int_SH[2] ), .Y(n69) );
  MXI2X1 U132 ( .A(n70), .B(n92), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][9] ) );
  MXI2X1 U133 ( .A(\u2/sll_46/ML_int[2][9] ), .B(\u2/sll_46/ML_int[2][5] ), 
        .S0(\u2/sll_46/temp_int_SH[2] ), .Y(n70) );
  MXI2X1 U134 ( .A(n71), .B(n93), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][10] ) );
  MXI2X1 U135 ( .A(\u2/sll_46/ML_int[2][10] ), .B(\u2/sll_46/ML_int[2][6] ), 
        .S0(\u2/sll_46/temp_int_SH[2] ), .Y(n71) );
  MXI2X1 U136 ( .A(n72), .B(n94), .S0(\u2/sll_46/temp_int_SH[3] ), .Y(
        \u2/sll_46/ML_int[4][11] ) );
  NAND2X1 U137 ( .A(\u2/sll_46/temp_int_SH[2] ), .B(\u2/sll_46/ML_int[2][7] ), 
        .Y(n72) );
  INVX1 U138 ( .A(\u1/sll_32/SHMAG[0] ), .Y(\u1/sll_32/temp_int_SH[0] ) );
  INVX1 U139 ( .A(n74), .Y(\u1/sll_32/temp_int_SH[3] ) );
  AOI31X1 U140 ( .A0(\u1/N9 ), .A1(\u1/N7 ), .A2(\u1/N8 ), .B0(n76), .Y(n75)
         );
  OAI31X1 U141 ( .A0(\u1/N7 ), .A1(\u1/N9 ), .A2(\u1/N8 ), .B0(n76), .Y(n77)
         );
  INVX1 U142 ( .A(\u1/N10 ), .Y(n76) );
  INVX1 U143 ( .A(n73), .Y(\u1/sll_32/temp_int_SH[2] ) );
  INVX1 U144 ( .A(\u1/sll_32/SHMAG[1] ), .Y(\u1/sll_32/temp_int_SH[1] ) );
  AOI21X1 U145 ( .A0(\u1/N6 ), .A1(n79), .B0(n78), .Y(\u1/sll_32/SHMAG[4] ) );
  NAND2X1 U146 ( .A(n12), .B(n13), .Y(n11) );
  INVX1 U147 ( .A(n12), .Y(n10) );
  NAND2X1 U148 ( .A(n96), .B(\u2/sll_46/SHMAG[3] ), .Y(n95) );
  INVX1 U149 ( .A(\u2/sll_46/SHMAG[0] ), .Y(\u2/sll_46/temp_int_SH[0] ) );
  INVX1 U150 ( .A(\u2/sll_46/SHMAG[3] ), .Y(\u2/sll_46/temp_int_SH[3] ) );
  INVX1 U151 ( .A(n86), .Y(n90) );
  AOI31X1 U152 ( .A0(\u2/N7 ), .A1(\u2/N5 ), .A2(\u2/N6 ), .B0(n87), .Y(n86)
         );
  INVX1 U153 ( .A(n88), .Y(n89) );
  OAI31X1 U154 ( .A0(\u2/N5 ), .A1(\u2/N7 ), .A2(\u2/N6 ), .B0(n87), .Y(n88)
         );
  NAND2X1 U155 ( .A(\u2/sll_46/ML_int[2][0] ), .B(\u2/sll_46/SHMAG[2] ), .Y(
        n91) );
  NAND2X1 U156 ( .A(\u2/sll_46/ML_int[2][1] ), .B(\u2/sll_46/SHMAG[2] ), .Y(
        n92) );
  NAND2X1 U157 ( .A(\u2/sll_46/ML_int[2][2] ), .B(\u2/sll_46/SHMAG[2] ), .Y(
        n93) );
  NAND2X1 U158 ( .A(\u2/sll_46/ML_int[2][3] ), .B(\u2/sll_46/SHMAG[2] ), .Y(
        n94) );
  INVX1 U159 ( .A(\u2/N8 ), .Y(n87) );
  INVX1 U160 ( .A(\u2/sll_46/SHMAG[2] ), .Y(\u2/sll_46/temp_int_SH[2] ) );
  INVX1 U161 ( .A(\u2/sll_46/SHMAG[1] ), .Y(\u2/sll_46/temp_int_SH[1] ) );
  AOI21X1 U162 ( .A0(\u1/N3 ), .A1(n79), .B0(n78), .Y(\u1/sll_32/SHMAG[1] ) );
  NAND2X1 U163 ( .A(n14), .B(n15), .Y(n12) );
  OAI21XL U164 ( .A0(n18), .A1(n19), .B0(\u1/N36 ), .Y(n14) );
  OAI21XL U165 ( .A0(n16), .A1(n17), .B0(n13), .Y(n15) );
  NAND4X1 U166 ( .A(\u1/re[9] ), .B(\u1/re[8] ), .C(\u1/re[7] ), .D(
        \u1/re[14] ), .Y(n19) );
  OR4X2 U167 ( .A(\u1/re[14] ), .B(\u1/re[7] ), .C(\u1/re[8] ), .D(\u1/re[9] ), 
        .Y(n16) );
  OAI2BB1X1 U168 ( .A0N(\u1/re[1] ), .A1N(n10), .B0(n11), .Y(\u1/N30 ) );
  OAI2BB1X1 U169 ( .A0N(\u1/re[2] ), .A1N(n10), .B0(n11), .Y(\u1/N31 ) );
  OAI2BB1X1 U170 ( .A0N(\u1/re[3] ), .A1N(n10), .B0(n11), .Y(\u1/N32 ) );
  OAI2BB1X1 U171 ( .A0N(\u1/re[4] ), .A1N(n10), .B0(n11), .Y(\u1/N33 ) );
  OAI2BB1X1 U172 ( .A0N(\u1/re[5] ), .A1N(n10), .B0(n11), .Y(\u1/N34 ) );
  OAI2BB1X1 U173 ( .A0N(\u1/re[6] ), .A1N(n10), .B0(n11), .Y(\u1/N35 ) );
  OR4X2 U174 ( .A(\u1/re[10] ), .B(\u1/re[11] ), .C(\u1/re[12] ), .D(
        \u1/re[13] ), .Y(n17) );
  NAND4X1 U175 ( .A(\u1/re[13] ), .B(\u1/re[12] ), .C(\u1/re[11] ), .D(
        \u1/re[10] ), .Y(n18) );
  INVX1 U176 ( .A(\u1/N36 ), .Y(n13) );
  OR2X2 U177 ( .A(\u1/re[0] ), .B(n12), .Y(\u1/N29 ) );
  AOI21X1 U178 ( .A0(\u2/N0 ), .A1(n90), .B0(n89), .Y(\u2/sll_46/SHMAG[0] ) );
  AOI21X1 U179 ( .A0(\u2/N2 ), .A1(n90), .B0(n89), .Y(\u2/sll_46/SHMAG[2] ) );
  AOI21X1 U180 ( .A0(\u2/N3 ), .A1(n90), .B0(n89), .Y(\u2/sll_46/SHMAG[3] ) );
  AND2X1 U181 ( .A(\u2/sll_46/temp_int_SH[2] ), .B(\u2/sll_46/ML_int[2][8] ), 
        .Y(\u2/sll_46/ML_int[3][12] ) );
  AND2X1 U182 ( .A(\u2/sll_46/temp_int_SH[2] ), .B(\u2/sll_46/ML_int[2][9] ), 
        .Y(\u2/sll_46/ML_int[3][13] ) );
  AND2X1 U183 ( .A(\u2/sll_46/temp_int_SH[1] ), .B(\u2/sll_46/ML_int[1][7] ), 
        .Y(\u2/sll_46/ML_int[2][9] ) );
  AND2X1 U184 ( .A(\u2/sll_46/temp_int_SH[2] ), .B(\u2/sll_46/ML_int[2][10] ), 
        .Y(\u2/sll_46/ML_int[3][14] ) );
  AND2X1 U185 ( .A(\u2/sll_46/temp_int_SH[1] ), .B(\u2/sll_46/MR_int[1][7] ), 
        .Y(\u2/sll_46/ML_int[2][10] ) );
  AND2X1 U186 ( .A(\u2/add_46/carry[7] ), .B(mark_a[7]), .Y(\u2/N8 ) );
  XOR2X1 U187 ( .A(mark_a[7]), .B(\u2/add_46/carry[7] ), .Y(\u2/N7 ) );
  AND2X1 U188 ( .A(\u2/add_46/carry[6] ), .B(mark_a[6]), .Y(
        \u2/add_46/carry[7] ) );
  XOR2X1 U189 ( .A(mark_a[6]), .B(\u2/add_46/carry[6] ), .Y(\u2/N6 ) );
  AND2X1 U190 ( .A(\u2/add_46/carry[5] ), .B(mark_a[5]), .Y(
        \u2/add_46/carry[6] ) );
  XOR2X1 U191 ( .A(mark_a[5]), .B(\u2/add_46/carry[5] ), .Y(\u2/N5 ) );
  AND2X1 U192 ( .A(\u2/add_46/carry[4] ), .B(mark_a[4]), .Y(
        \u2/add_46/carry[5] ) );
  XOR2X1 U193 ( .A(mark_a[4]), .B(\u2/add_46/carry[4] ), .Y(\u2/N4 ) );
  AND2X1 U194 ( .A(\u2/add_46/carry[3] ), .B(mark_a[3]), .Y(
        \u2/add_46/carry[4] ) );
  XOR2X1 U195 ( .A(mark_a[3]), .B(\u2/add_46/carry[3] ), .Y(\u2/N3 ) );
  AND2X1 U196 ( .A(\u2/add_46/carry[2] ), .B(mark_a[2]), .Y(
        \u2/add_46/carry[3] ) );
  XOR2X1 U197 ( .A(mark_a[2]), .B(\u2/add_46/carry[2] ), .Y(\u2/N2 ) );
  AND2X1 U198 ( .A(\u1/sll_32/temp_int_SH[2] ), .B(\u1/sll_32/ML_int[2][10] ), 
        .Y(\u1/sll_32/ML_int[3][14] ) );
  AND2X1 U199 ( .A(\u1/sll_32/temp_int_SH[1] ), .B(\u1/sll_32/MR_int[1][7] ), 
        .Y(\u1/sll_32/ML_int[2][10] ) );
  XOR2X1 U200 ( .A(n64), .B(\u1/add_32/carry[7] ), .Y(\u1/N9 ) );
  AND2X1 U201 ( .A(\u1/add_32/carry[6] ), .B(d1[6]), .Y(\u1/add_32/carry[7] )
         );
  XOR2X1 U202 ( .A(d1[6]), .B(\u1/add_32/carry[6] ), .Y(\u1/N8 ) );
  AND2X1 U203 ( .A(\u1/add_32/carry[5] ), .B(d1[5]), .Y(\u1/add_32/carry[6] )
         );
  XOR2X1 U204 ( .A(d1[5]), .B(\u1/add_32/carry[5] ), .Y(\u1/N7 ) );
  AND2X1 U205 ( .A(\u1/add_32/carry[4] ), .B(d1[4]), .Y(\u1/add_32/carry[5] )
         );
  XOR2X1 U206 ( .A(d1[4]), .B(\u1/add_32/carry[4] ), .Y(\u1/N6 ) );
  AND2X1 U207 ( .A(\u1/add_32/carry[3] ), .B(d1[3]), .Y(\u1/add_32/carry[4] )
         );
  AND2X1 U208 ( .A(\u1/add_32/carry[2] ), .B(d1[2]), .Y(\u1/add_32/carry[3] )
         );
  INVX1 U209 ( .A(\u1/add_32/carry[2] ), .Y(\u1/N3 ) );
  AND2X2 U210 ( .A(n64), .B(\u1/sll_32/temp_int_SH[0] ), .Y(
        \u1/sll_32/MR_int[1][7] ) );
  AND2X2 U211 ( .A(\u2/N0 ), .B(\u2/sll_46/SHMAG[0] ), .Y(
        \u2/sll_46/ML_int[1][0] ) );
  AND2X2 U212 ( .A(mark_a[7]), .B(\u2/sll_46/temp_int_SH[0] ), .Y(
        \u2/sll_46/MR_int[1][7] ) );
  AND2X2 U213 ( .A(\u2/sll_46/ML_int[1][0] ), .B(\u2/sll_46/SHMAG[1] ), .Y(
        \u2/sll_46/ML_int[2][0] ) );
  AND2X2 U214 ( .A(\u2/sll_46/ML_int[1][1] ), .B(\u2/sll_46/SHMAG[1] ), .Y(
        \u2/sll_46/ML_int[2][1] ) );
  AND2X2 U215 ( .A(\u2/sll_46/ML_int[4][10] ), .B(n96), .Y(d2[10]) );
  AND2X2 U216 ( .A(\u2/sll_46/ML_int[4][11] ), .B(n96), .Y(d2[11]) );
  AND2X2 U217 ( .A(\u2/sll_46/ML_int[4][12] ), .B(n96), .Y(d2[12]) );
  AND2X2 U218 ( .A(\u2/sll_46/ML_int[4][13] ), .B(n96), .Y(d2[13]) );
  AND2X2 U219 ( .A(\u2/sll_46/ML_int[4][14] ), .B(n96), .Y(d2[14]) );
  AND2X2 U220 ( .A(\u2/sll_46/ML_int[4][8] ), .B(n96), .Y(d2[8]) );
  AND2X2 U221 ( .A(\u2/sll_46/ML_int[4][9] ), .B(n96), .Y(d2[9]) );
endmodule

Yes,there is no mark_a[0]!!
 

lostinxlation

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you don't have mark_a[0], but you have \u2/N0 which drives a mux in u2, don't you ?
I know it declares [7:0] mark_a, but it doesn't seem a big deal.
 

HolySaint

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lostinxlation said:
you don't have mark_a[0], but you have \u2/N0 which drives a mux in u2, don't you ?
I know it declares [7:0] mark_a, but it doesn't seem a big deal.

thank you.
i am clear now.

regards
 

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