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ohh...I think you didn't get my question....Sorry for so brief question, let me ask it again, why do we use symmetric inverters and buffers instead of normal inverters and buffers in clock tree synthesis????
Clock nets being of higher frequency are more sensitive with regard to timing - transition rise, fall times etc. Hence clock buffers have equal rise and fall slew rates, On the other hand, normal buffers are designed with p/n ratio such that sum of rise delay and fall delay is minimum (atleast for high speed libraries)
Reason for doing this(symmetricity) is to prevent duty cycle of clock signal from changing when it passes through a chain of clock buffers.
as you all know that goal of CTS is to meet skew target or in otherwords to achieve minimum skew.
To accomplish this we insert buffers in clock path. Now if buffers have different rise and fall time it will affect clock duty cycle... with this condition also tool can do skew optimization.... but it complicates the whole optimization process as tool has to deal with clock with different duty cycle at different flop paths.
If buffer delays are same only thing tool has to do is to balance the delay by inserting buffers.... skew balancing algorithm may be local skew or global skew optimization as you select it.
If a clock tree is synthesized with all buffers, and an inverted clock is not needed, then an imbalanced buffer does not impact clock duty cycle. The main reason symmetric buffers are used in a clock tree is power. The clock is the most active signal in a design and since slow transitions increases power, clock buffers are symmetric with minimized slews to minimize power.