d3m0nxxl
Newbie level 1
Hi,
when simulating an ASIC design, i try to easily switch between RTL simulation and gate level simulation. (using ModelSim)
For RTL simulation, I have to specify generic parameters. While simulating the netlist, the generic parameters are not longer present.
For the moment, i have to comment in/out the generics.
I can not use generate statements, as the generics have to be specified in the component as well.
As i know, preprocessor commands like 'ifdef are only valid in verilog, but I use VDHL as the system environment.
Does anyone have an idea, how to do this? Is it possible for example, somehow to ignore the error message for not bound generics?
Thanks in advance!
when simulating an ASIC design, i try to easily switch between RTL simulation and gate level simulation. (using ModelSim)
For RTL simulation, I have to specify generic parameters. While simulating the netlist, the generic parameters are not longer present.
For the moment, i have to comment in/out the generics.
I can not use generate statements, as the generics have to be specified in the component as well.
As i know, preprocessor commands like 'ifdef are only valid in verilog, but I use VDHL as the system environment.
Does anyone have an idea, how to do this? Is it possible for example, somehow to ignore the error message for not bound generics?
Thanks in advance!