Switching activity factor in cmos

[Manuv16589]

Hi there,
The dynamic power dissipation in a Cmos circuit is given by
P=a*C*Vdd(square)*f
where a is the switching activity factor which is the probability of output switching from 0 to 1. Can somebody give more details? It would be more precise if you could explain with an example. Thanks in advance

 

[iop95]

Various block/gates from an IC may have different switching probability over time. For example, clock generator have a=1, mean switch all time, a counter (part of counter) may have switchs (transitions) at 1/10 from clock or 1/100, so a=0.1 or 0.01 respectively. In such way knowing working mode for each gate, know a, so may calculate power disipation for an IC or other device.

 

[Manuv16589]

Thanks iop95
Can u explain switching factor taking 2 input and gate as an example so that it will more clear to me

 

[iop95]

This factor is not related of a gate with 2 or more inputs, it's related to what do this gate, more exactly how many swithching (transitions) made per unit time. More details may find here: https://www.google.ro/url?sa=t&rct=...yPXQDw&usg=AFQjCNEtwaM2doKB77yaTMsYvwbl_ISEbQ