Switch time is commonly refered to Rise or Fall time of a signal. There are various definitions for this time. The one I follow is "this is the time taken by a signal to reach 90% of its peak voltage level starting from 10%" Fall time is the converse of this. Rise time or Fall time is affected in a PCB mainly by loading on a driver. In constraint manager you can put a cap on this value, which inturn will put a cap on maximum trace capacitance.
Settle delay is the time taken by a signal to settle down in it's permissible peak or least voltage level after reaching that level.
For settle delay calculation, does any parameters required? Because, if there are ringing voltages or overshoot/undershoot condition at receiver end then how to minimize this delay?