switch case in nexys2 board

[xilinx1001]

Hi,

I am working on Nexys2 board

I am writing the code that shows:

the binary value of first 4 switches on one 7 segment display

binary value of next 4 switches on on another 7 segment display


My idea is to use arrays inside a switch

Can anyone suggest me something about this

 

[TrickyDicky]

What arrays? what swtich? are you talking about a physical switch or HDL code?
I suggest asking better questions.

 

[xilinx1001]

Hi,
Thanks for your reply
What I mean is
I need to display the binary value of the first 4 physical switches of the board on one 7 segment display
binary value of next 4 physical switches of the board on on another 7 segment display

Any idea about writing the code for this

 

[TrickyDicky]

Yes I do, thanks.
What are your ideas?

 

[xilinx1001]

Yes I do, thanks.
What are your ideas?

My idea is to use mux(multiplexer)

 

[TrickyDicky]

well, Im sure thats a good start
Away you go - get coding. Come back when you're having problems.

 

[xilinx1001]

well, Im sure thats a good start
Away you go - get coding. Come back when you're having problems.

----------------------------------------------------------------------------------

I am using 2 entities and 2 architectures in my code. I am having errors in my code. The bold lines in the code are erros. The errors are given below the code

code:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL

entity s0 is
* * Port ( switches : in *STD_LOGIC_VECTOR (3 downto 0);
* * * *switches1 : in *STD_LOGIC_VECTOR (3 downto 0);
*
* * * * * *sevenseg : out *STD_LOGIC_VECTOR (6 downto 0);

* * * * * *anodes: out *STD_LOGIC_VECTOR (3 downto 0));

*
end s0;
entity s1 is
* * Port ( switches1 : in STD_LOGIC_VECTOR (7 downto 4);
* * * *--switches1 : in *STD_LOGIC_VECTOR (3 downto 0);
*
* * * * * *sevenseg : out STD_LOGIC_VECTOR (6 downto 0);
-- *sevenseg1 : out *STD_LOGIC_VECTOR (6 downto 0);
* * * * * *anodes: out STD_LOGIC_VECTOR (3 downto 0));
-- leds: out *STD_LOGIC_VECTOR (7 downto 0)*
*
end s1;


architecture Behavioral of s0 is
process(sevenseg,anodes)
begin




*sevenseg <= "0100100" when x"0",
"1111001" when x"1",
* * * * * * *"0100100" when x"2",
* * * * * * *"0110000" when x"3",
* * * * * * *"0011001" when x"4",*
* * * * * * *"0010010" when x"5",
* * * * * * *"0000010" when x"6",
* * * * * * *"1111000" when x"7",
* * * * * * *"0000000" when x"8",
* * * * * * *"0010000" when x"9",
"0001000" when x"A",
"0000011" when x"B",
"1000110" when x"C",
"0100001" when x"D",
* *"0000110" when x"E",*
"0001110" when others;




anodes <= "1110";*

end process;


architecture Behavioral of s1 is
process(sevenseg,anodes)
begin
--if reset='1' then*
*sevenseg <= "0100100" when x"0",
"1111001" when x"1",
* * * * * * *"0100100" when x"2",
* * * * * * *"0110000" when x"3",
* * * * * * *"0011001" when x"4",*
* * * * * * *"0010010" when x"5",
* * * * * * *"0000010" when x"6",
* * * * * * *"1111000" when x"7",
* * * * * * *"0000000" when x"8",
* * * * * * *"0010000" when x"9",
"0001000" when x"A",
"0000011" when x"B",
"1000110" when x"C",
"0100001" when x"D",
* *"0000110" when x"E",*
"0001110" when others;

anodes <= "1101";*

end process;

end Behavioral;

Errors:
"Line 47. Undefined symbol 'STD_LOGIC_VECTOR'.
" Line 47. STD_LOGIC_VECTOR: Undefined symbol (last report in this block)
" Line 60. parse error, unexpected PROCESS

 

[std_match]

For each entity, you must repeat the library stuff (the "library" and "use" lines).
And please delete the std_logic_arith and std_logic_unsigned libraries, and start using numeric_std instead, before you are stuck with bad habits.
For the code you show, you only need std_logic_1164.

Edit:
You should not have two identical entities. What you want is one entity for decoding a digit, and then use two instances of it in an outer entity.
The sensitivity list of a process should only list the inputs, not the outputs.

 

[xilinx1001]

Hi,

Thanks for your reply

How do I know which std_logic I need to use

I mean std_logic_arith or std_logic_unsigned libraries or numeric_std instead,

 

[TrickyDicky]

std_logic_arith and std_logic_unsigned are non-standard VHDL libraries. Easy answer is never use them. Only use numeric_std.

 

[mrflibble]

Some inspiration: https://www.edaboard.com/threads/285419/

No I don't have ready to go code. The above thread is it. Have fun with the educational moment!