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[SOLVED] Suppressing ModelSim Transcript window messages

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dpaul

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I am using ModelSim DE-64 10.5.

The design has a DDR3 memory simulation model due to which I get the following messages in the Transcript window.
Code:
# mio_pf_tb.sdram.data_task: at time 4191 ns ERROR: DQS_N bit           1 latching edge required during the preceding clock period.
# mio_pf_tb.sdram.data_task: at time 4192 ns ERROR: DQS   bit           0 latching edge required during the preceding clock period
# mio_pf_tb.sdram.data_task: at time 4192 ns ERROR: DQS   bit           1 latching edge required during the preceding clock period
# mio_pf_tb.sdram.data_task: at time 4192 ns ERROR: DQS_N bit           0 latching edge required during the preceding clock period
# mio_pf_tb.sdram.data_task: at time 4192 ns ERROR: DQS_N bit           1 latching edge required during the preceding clock period

I want to suppress only the above type of messages.
From the ModelSim UG, I came to know about the 'suppress' command that can be put inside the modelsim.ini file.

UG excerpt-
Section [msg_system]
This variable suppresses the listed message numbers and/or message code strings (displayed in square brackets).

Syntax
suppress = <msg_number>…
Arguments
• The arguments are described as follows:
o <msg_number>… — An unlimited list of message numbers, comma separated.
You can override this variable setting by specifying the vcom, vlog, or vsim
command with the -suppress argument.


Basically it is not clear to me how exactly this command can be used. I do not have any <message_number> here, it is just a custom string. I have tried....
suppress = <# mio_pf_tb.sdram.data_task: at time>
which does not work.

Any help on how to suppress the above messages?
 

Looks like model generated messages. Did you search for the respective message text in the source?
 

I've seen these types of messages from DDR# models in the past.

They normally show up at the beginning of a simulation sometime after reset until the controller starts initializing the DDR. One option is to find the offending code in the model and add in a control to enable/disable the corresponding $display task. I connect that display control to either a port on the model or add a task to control it. If I add a task the default is turning off the display and you can enable it later in the simulation to make sure that the DDR# controller is working correctly.
 
Looks like model generated messages. Did you search for the respective message text in the source?
No I didn't, I though I could play around with MSim settings and suppress those messages.

I've seen these types of messages from DDR# models in the past.
They normally show up at the beginning of a simulation sometime after reset until the controller starts initializing the DDR. One option is to find the offending code in the model and add in a control to enable/disable the corresponding $display task. I connect that display control to either a port on the model or add a task to control it. If I add a task the default is turning off the display and you can enable it later in the simulation to make sure that the DDR# controller is working correctly
.
I will tell you when these messages show up. The DDR3 is written in KB chunks. After a certian amount of KB is written, the DDR3 is read out. Theses messages appear when the DDR3 is being read.

Ok, then it seems I have to look in to the DDR3 model, find the place where they are coded and do something with it.
Thank you for the idea ads-ee.
 

Well if they are showing up on the read then they may be a issue if the controller you are using is violating some specification of the DDR3.

Most DDR3 models I've used will corrupt the data (make X) if you violate some timing spec, but I've seen some that don't and just issue a warning. I guess it depends on the model writers. I've also seen models (not a DDR3) that actually have checks that violate the timing specs in their datasheet. So I would look at the model and make sure you can actually ignore this warning, before editing the code to remove it.
 

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