supply voltage variation

[ramaswami]

voltage variation

hi all ,
i have an architecture and verilog codes for all the blocks in that arch.
if i want to implement multiple voltage scaling techq to that which tool
will allow to vary VDD to find out delays at lower or higher VDD

 

[tariq786]

voltage variation

You have to do HSPICE simulation to do that. For that you need to convert your verilog circuit to HSPICE format, which could be a manual labor. Once you have done it, then its a piece of cake.

 

[mehrdadfeller]

voltage variation main supply

What is your design size?
You can convert your design after synthesis to HSPICE netlist automatically using Cadence IC6.1. Once you get the netlist, simply change the VDD and simulate it. If your design has more than 10,000 transistors, the HSPICE can take a long time.

Alternatively, you can make new library for synthesis/map with modified delays obtained from individually simulating cells in the library for different VDDs. The latter solution is a bit harder.

Mehrdad

 

[ramaswami]

voltage variation measurement

What is your design size?
You can convert your design after synthesis to HSPICE netlist automatically using Cadence IC6.1. Once you get the netlist, simply change the VDD and simulate it. If your design has more than 10,000 transistors, the HSPICE can take a long time.

Alternatively, you can make new library for synthesis/map with modified delays obtained from individually simulating cells in the library for different VDDs. The latter solution is a bit harder.

Mehrdad

thankq Mehrdad, i will try. If u have any other idea plz let me know..