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Supply Voltage Glitch Simulation

borabilgic

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Hi, I want to simulate VDD glitch. For example I want to raise 1.2V VDD to 4-5 Volts for tens of microseconds and lower back to 1.2V. Suppose I have a high rise and fall time pulse generator (200-500 picoseconds). My concern is that some digital ICs (like CPUs) have some capacitors on them to filter supply parasitics and serve as charge reservoir. Do these capacitors hinder the high rise and fall time of the signal generator because of their time constants? Can I still get a fast changing VDD in spite of the capacitors? Thank you.
 

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Maybe I'm just dense, but what does this have to do with FPGAs? Are you trying to run Verilog/VHDL simulations of voltage glitches? Can't be done.
 

danadakk

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Yes Caps would, but keep in mind they do have some esr, some L.

What is steady state load current that has to be switched ?

There are MOSFET gate drivers that achieve tens of nS driving 1000 - 2000 pF,
but your board must have both bulk and ceramic, several 1000x in C load I think.

There are avalanche approaches that can achieve high speed of dropping a supply.
the control loop fro most board level regulators is slow enough that rapid discharge
of Vdd might be possible.

I did a bench design many years ago that had to switch HV into a load, but not as much C
as you are facing. Basically cut the top several TO3 NPN switching transistors, and used a
flash tube(avalanche) to get them to switch. Somewhere in the 10's of uS if i recall were results.
600 volts I think.

Use Q = C x V, I = C x dV / dT and add up your board C to see what slew rate you would need.



Regards, Dana.
 

dick_freebird

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A stiff pulsed source would just "get it done"
but most pulse generators are 50-ohm output.
That all has to do with the real world.

In simulation I believe you are chasing a
ghost because your 1.2V devices will all
punch through at 4-5V applied, yet MOS
models as a rule have no valid emulation
of breakdown - you're lucky if you even
get a warning flag in the report file. When
I was doing ESD design I would add a zener
and resistor to the macromodel layer, to
get a match to TLP data.

In reality if you punch through every device
in the logic core, you'll probably lose bond
wires (if chip-and-wire assembly) or bussing
to fusing-level currents.

If there is internal explicit capacitance (like
brazed to the package body) this value ought
to appear somewhere in the product docs.
Then you could add elements to model it,
and model the source impedance and
timing of the source, to get fidelity on the
threat waveform at the part.

But your MOS models are still likely to give
you nothing useful, on the "victim" side.
 

borabilgic

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A stiff pulsed source would just "get it done"
but most pulse generators are 50-ohm output.
Hi Dick,
What is a stiff pulsed source?
--- Updated ---

There are MOSFET gate drivers that achieve tens of nS driving 1000 - 2000 pF,
but your board must have both bulk and ceramic, several 1000x in C load I think.
Hi Dana,
I could not get what you ment above. Can you explain a little more? Thank you.
--- Updated ---

Maybe I'm just dense, but what does this have to do with FPGAs? Are you trying to run Verilog/VHDL simulations of voltage glitches? Can't be done.
I just want to apply a fast changing VDD to a chip (CPU, MCU, FPGA etc.). I just want to know whether it is possible or not? I mean the capacitances at supply pins would allow me to do it or not.
 
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danadakk

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There are MOSFET gate drivers that achieve tens of nS driving 1000 - 2000 pF,
but your board must have both bulk and ceramic, several 1000x in C load I think.

I guess that was a little cryptic.

On your board you must have both bulk C, like tantalums, uF range, in parallel with ceramic
C, typically .01 or .1 uF.

MOSFET gate drivers are ICs design to drive a lot of C load rapidly, as MOSFETs have
a lot of gate C, ranging from 100's of pF to a couple thousand pF. These drivers have
high peak current capability, for short periods of time, just the thing for fast Tr and Tf
times. But your board does have more than a couple of thousand pf typically, so not
sure how these drivers would handle that, eg. could they produce uS of Tr and Tf with
uF kinds of loads ? Look at some gate driver datasheets, use the selector tools at Digikey,
look at parts .= 10A drive current. I see parts, for 100K pF, that can do fall times ~ 300 nS, so
look at typical graphs to see what higher C performance looks like.


Regards, Dana.
 

dick_freebird

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Hi Dick,
What is a stiff pulsed source?

"Stiff" means high current compliance, no or
trivial series resistance. Like a power supply
(which unfortunately is slow). An ideal voltage
source is "stiff", no amount of current will "bend"
the voltage value it imposes.

Which of these matters to you depends on
what you meant by "simulate" - SPICE, or bench
electrical.

A signal generator with a 50-ohm Zout is not
"stiff". Your current "bends" at 50mV/mA.

If you want to smack a capacitive load around,
Rout*Cload is your RC time constant and close
enough to achievable risetime. A 50-ohm sig
gen and a 0.01uF decoupling cap would limit
achievable rietimes to half a microsecond or so
(0-70%). Double that if you call it 10-90% risetime
criterion as that's about 2 tau.
 

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